PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

Blue Gene/Q: design for sustained multi-petaflop computing

Abstract: The Blue Gene/Q system represents the third generation of optimized high-performance computing Blue Gene solution servers and provides a platform for continued growth in HPC performance and capability. Blue Gene/Q started with a new design of the hardware platform, while retaining and significantly expanding an established, trusted and successful software environment.To deliver a system that enables users to fully exploit the promise of high-performance computing for both traditional HPC applications and new commercial application areas, the Blue Gene/Q system architecture combines hardware and software innovations to overcome traditional bottlenecks, most famously the memory and power walls which have become emblematic of modern computing systems. At the same time, to deliver a platform for sustainable petascale computing, and beyond to exascale, we had to address a new set of "walls" with the many innovations described below: a scalability wall, a communication wall, and a reliability wall.The new Blue Gene/Q system increases overall system performance with a new node architecture: Each node offers more thread-level-parallelism with a coherent SMP node consisting of eighteen 64-bit PowerPC cores with 4-way simultaneous multithreading. Each core provides for better exploitation of data-level parallelism with a new 4-way quad-vector processing unit (QPU). The memory subsystem integrates memory speculation support which can be used to implement both Transactional Memory and Speculative Execution programming models.The compute nodes are connected in a five dimensional torus configuration using 10 point-to-point links, and a total network bandwidth of 44 GB/s per node. The on-chip messaging unit provides an optimized interface between the network routing logic and the memory subsystem, with enough bandwidth to keep all the links busy. It also offloads communication protocol processing by implementing collective broadcast and reduction operations, including integer and floating point sum, min and max.Built on the Blue Gene hardware design is an efficient software stack that builds on several generations of Blue Gene software interfaces, while extending these capabilities and adding new functions to support new hardware capabilities. The hardware functions were designed with a focus on providing efficient primitives upon which to build the rich software environment.To ensure reliable operation of a petascale system, reliability has to be a pervasive design consideration. At the architecture level, new QPX store-and-indicate instructions support the detection of programming errors. To ensure reliable operation in the presence of transient faults, we conducted exhaustive single event upset simulations based on fault injection into the simulated design. The operating system was structured to use firmware in a small on-chip boot eDRAM to avoid silent system hangs.Together, the hardware and software innovations pioneered in Blue Gene/Q give application developers a platform and framework to develop and deploy sustained petascale computing applications. These petascale applications will allow its users to make new scientific discoveries and gain new business insights, which will be the true measure of the success of the new Blue Gene/Q systems.

Error Detection Enhancement in PowerPC Architecture-based Embedded Processors

Abstract: This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE) This technique is based on the branch trace exception feature available in the PowerPC processors family for debugging purposes This technique traces the target addresses of program branches at run-time and compares them with reference target addresses to detect possible violations caused by transient faults The reference target addresses are derived by a preprocessor from the source program To enhance the error detection coverage, three other mechanisms, ie, Machine Check Exception, System Trap Instructions and Work Load Timer are combined with the Branch Trace Exception mechanism The proposed technique is experimentally evaluated on a 32-bit PowerPC microcontroller using software implemented fault injection (SWIFI) and Power Supply Disturbances fault injection (PSD) A total of 6,000 faults were injected in microcontroller to measure the error detection coverage of the proposed control flow checking technique The experimental results show that this technique detects about 952% of transient errors in software implemented fault injection method and 964% of transient errors in power supply disturbances fault injection method

Simple and effective array prefetching in Java

Abstract: Java is becoming a viable choice for numerical algorithms due to the software engineering benefits of object-oriented programming. Because these programs still use large arrays that do not fit in the cache, they continue to suffer from poor memory performance. To hide memory latency, we describe a new unified compile-time analysis for software prefetching arrays and linked structures in Java. Our previous work uses data-flow analysis to discover linked data structure accesses, and here we present a more general version that also identifies loop induction variables used in array accesses. Our algorithm schedules prefetches for all array references that contain induction variables. We evaluate our technique using a simulator of an out-of-order superscalar processor running a set of array-based Java programs. Across all our programs, prefetching reduces execution time by a geometric mean of 23%, and the largest improvement is 58%. We also evaluate prefetching on a PowerPC processor, and we show that prefetching reduces execution time by a geometric mean of 17%. Traditional software prefetching algorithms for C and Fortran use locality analysis and sophisticated loop transformations. Because our analysis is much simpler and quicker, it is suitable for including in a just-in-time compiler. We further show that the additional loop transformations and careful scheduling of prefetches used in previous work are not always necessary for modern architectures and Java programs.

A high density, high performance MCM-D/C package: a design, electrical, and process perspective

Abstract: This paper describes a state-of-the-art seven chip MCM-D/C package currently under production for use as a processor module for the high end of IBM's AS/400 Advanced Series with PowerPC technology. Physical design, process, and electrical design (characterization) is described, and trade-offs made between them are discussed.

Computational Core Design of a Wireless Structural Health Monitoring System

Abstract: Complementing recent advances made in the field of structural health monitoring and damage detection, the concept of a wireless sensing network with distributed computational power is proposed. The fundamental building block of the proposed sensing network is a wireless sensing unit capable of acquiring measurement data, interrogating the data and transmitting the data in real-time to the network. To perform the computationally intensive task of damage detection, an advanced PowerPC computational core is chosen. First, a layer of software comprised of various device driver modules is developed to operate the various hardware subsystems of the wireless sensing unit. Additional software is then designed for embedment that can locally execute a time-series based damage detection algorithm.