PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

Modeling the influence of multilevel interconnect on chip performance

Abstract: The purpose of this work is the development of a design and evaluation tool, named "Rensselaer Interconnect Performance Estimator" (RIPE), to analyze the impact on size, wireability, performance, power dissipation and reliability of single chip microprocessors as a function of interconnect, device, circuit, design and architectural parameters. A study of existing microprocessors and their design practices has been done to identify the parameters required to model such a system to the first order. As a result, a system model encompassing memory, core logic and I/O circuitry has been presented. Compared to earlier performance estimators, such as SUSPENS and Sai-Halasz' cycle time estimator, RIPE can accurately predict the overall performance of current microprocessor systems. For the three major microprocessor architectures: DEC, PowerPC and Intel, RIPE results indicated agreement within 10% on key parameters such as transistor count, area, wiring levels, clock frequency and power dissipation. The RIPE model has also been used to study the SIA (Semiconductor Industry Association) Roadmap predictions and technology characteristics for future microprocessor systems. The results indicate that for the 0.10 $\mu$m generation, the performance of interconnect limits overall performance and a combination of performance improving design techniques, such as interconnect length limiting floorplans, new interconnect materials and architectures, are needed to be able to meet future performance goals.

A self-reconfigurable platform for general purpose image processing systems on low-cost spartan-6 FPGAs

Abstract: There is still no partial reconfiguration tool support on low-cost Field Programmable Gate Arrays (FPGAs) such as old-fashioned Spartan-3 and state-of-the-art Spartan-6 FPGA families by Xilinx. This forces the designers and engineers, who are using the partial reconfiguration capability of FPGAs, to use expensive families such as Virtex-4, Virtex-5 and Virtex-6 which are officially supported by partial reconfiguration (PR) software. Moreover, Xilinx still does not offer a portable, dedicated self-reconfiguration engine for all of the FPGAs. Self-reconfiguration is achieved with general-purpose processors such as MicroBlaze and PowerPC which are too overqualified for this purpose. In this study, we propose a new self-reconfiguration mechanism for Spartan-6 FPGAs. This mechanism can be used to implement large and complex designs on small FPGAs as chip area can be dramatically reduced by exploiting the dynamic partial reconfiguration feature for on-demand functionality loading and maximal utilization of the hardware. This approach is highly attractive for designing low-cost compute-intensive applications such as high performance image processing systems. For Spartan-6 FPGAs, we have developed hard-macros and exploited the self-reconfiguration engine, compressed Parallel Configuration Access Port (cPCAP) [1], that we designed for Spartan-3. The modified cPCAP core with block RAM controller, bitstream decompressor unit and Internal Configuration Access Port (ICAP) Finite State Machine (FSM) occupies only about 82 of 6,822 slices (1.2% of whole device) on a Spartan-XC6SLX45 FPGA and it achieves the maximum theoretical reconfiguration speed of 200MB/s (ICAP, 16-bit at 100MHz) proposed by Xilinx. We have also implemented a Reconfigurable Processing Element (RPE) whose arithmetic unit can be reconfigured on-the-fly. Multiple RPEs can be utilized to design a General Purpose Image Processing System (GPIPS) that can implement a number of different algorithms during runtime. As an illustrative example, we programmed the GPIPS on Spartan-6 for switching between two applications on-demand such as two-dimensional filtering and block-matching.

A Reconfigurable System Approach to the Direct Kinematics of a 5 D.o.f Robotic Manipulator

Abstract: Hardware acceleration in high performance computer systems has a particular interest for many engineering and scientific applications in which a large number of arithmetic operations and transcendental functions must be computed. In this paper a hardware architecture for computing direct kinematics of robot manipulators with 5 degrees of freedom (5 D.o.f) using floating-point arithmetic is presented for 32, 43, and 64 bit-width representations and it is implemented in Field Programmable Gate Arrays (FPGAs). The proposed architecture has been developed using several floating-point libraries for arithmetic and transcendental functions operators, allowing the designer to select (pre-synthesis) a suitable bit-width representation according to the accuracy and dynamic range, as well as the area, elapsed time and power consumption requirements of the application. Synthesis results demonstrate the effectiveness and high performance of the implemented cores on commercial FPGAs. Simulation results have been addressed in order to compute the Mean Square Error (MSE), using the Matlab as statistical estimator, validating the correct behavior of the implemented cores. Additionally, the processing time of the hardware architecture was compared with the same formulation implemented in software, using the PowerPC (FPGA embedded processor), demonstrating that the hardware architecture speeds-up by factor of 1298 the software implementation.

PPCMatrix: a PowerPC dotmatrix program to compare large genomic sequences against protein sequences

Abstract: Summary : An interactive dotmatrix program for the MacOS was designed that allows comparison of DNA to protein sequences using nested 3-frame translations. Availability : Shareware, available at http://copan.bioz.unibas.ch/software/ Contact : burglin@ubaclu. unibas.ch

High performance network tester and the testing method thereof

Abstract: The invention discloses a high performance network tester and a testing method of the high performance network tester with the adoption of a FPGA+PowerPC+ARM framework. The network tester comprises a RJ45 interface, a transformer, a physical interface (PHY), an optical interface SFP, an FPGA, a PowerPC, an ARM and a display control device. The FPGA completes the generation and reception of testing flows, conducts analysis of a first layer message and a second layer message, controls the FPGA and surveys the first layer message and the second layer message; the PowerPC conducts analysis of a network protocol on a third layer or layers above; the ARM communicates with a computer to realize the display and control of entire equipment. According to the invention, the network tester puts together the advantages of three processors. The network tester is provided with high flexibility and is cost-effective to make. The tester is also compatible with a variety of interfaces and has strong expansibility.