PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

Arbitrating Instructions in an ρμ-Coded CCM

Abstract: In this paper, the design aspects of instruction arbitration in an ρμ-coded CCM are discussed. Software considerations, architectural solutions, implementation issues and functional testing of an ρμ-code arbiter are presented. A complete design of such an arbiter is proposed and its VHDL code is synthesized for the VirtexII Pro platform FPGA of Xilinx. The functionality of the unit is verified by simulations. A very low utilization of available reconfigurable resources is achieved after the design is synthesized. Simulations of an MPEG-4 case study suggest considerable performance speed-up in the range of 2,4-8,8 versus a pure software PowerPC implementation.

Architectural and multiprocessor design verification of the PowerPC 604 data cache

Abstract: The PowerPC 604 microprocessor has high performance 32-bit implementation, which is optimized to produce compact code while adhering to RISC philosophy. The PowerPC 604 microprocessor can sustain a maximum issue rate of 4 instructions per cycle. The data cache of the 604 is a 16 KB four-way set-associative non-blocking cache which contains MESI states (M: Modified, E: Exclusive-unmodified, S: Shared, I: Invalid), a reservation bit with its reservation address register, an independent snoop port, WIMG (W: cache write policy, I: cacheability, M: coherency mode, G: protection against speculative access) support logic, and parity bits. The 604 has an on-chip phase-locked loop to provide different Processor/Bus clock ratios to simplify the system design while using a 100 MHz processor clock. The data cache to BIU (Bus Interface Unit) interface can handle different Processor/Bus clock ratios. The architecture and multiprocessor verification for the PowerPC 604 data cache systematically checks the data cache architecture, logic, and implementation correctness and provides the assurance that the PowerPC 604 microprocessor's aggressive hardware and software implementation is carried out correctly in the uniprocessor and multiprocessor environment. >

Customizing CPU Instructions for Embedded Vision Systems

Abstract: This paper presents the customization of two processors: the Altera NIOS2 and the Tensilica Xtensa, for fundamental algorithms in embedded vision systems: the salient point extraction and the optical flow computation. Both can be used for image stabilization, for drones and autonomous robots. Using 16-bit floating-point instructions, the architecture optimization is done in terms of accuracy, speed and power consumption. A comparison with a PowerPC Altivec is also done.

Instruction Set Usage Analysis for Application-Spe cific Systems Design

Abstract: The manner in which the resources of a microprocess or are used affects its performance, power consumption and size. In this work we show how inc reasing the size of a processor's instruction set, in turn, increases the amount of hardware needed to impleme nt that processor. We also study how efficiently th e hardware resources of four processor architectures are used by measuring the static instruction set u tilization of a group of benchmark applications. The architect ures examined are the Intel x86, Intel x86-64, MIP S64, and PowerPC. We introduce the notions of instruction sexact cores and general-purpose cores, and then we use these concepts to propose a new measure of pro cessor resource utilization, core density. Based on the core density measure we show that on average 9 exact cor es are equivalent to a single general-purpose core in the existing architectures and that in particular insta nces this multiplier can go up to 48 exact cores.

Multiprocessor design verification for the PowerPC 620 microprocessor

Abstract: Multiprocessor design verification for the PowerPC 620 microprocessor was challenging due to the 620 Bus protocol complexity. The highly concurrent bus and level 2 (LS) cache interfaces, and the extensive system configurability. In order to verify this functionality, a combination of random and deterministic approaches were used. The Random Test Program Generator (RTPG) and the newly developed Stochastic Concurrent Program Generator (SCPG) tools were used for random verification. In the deterministic front, testcases in C were written to verify specific scenarios. In creating SCPG, we dealt with the design complexity and frequent design changes by abstracting areas of concern as simple languages, writing tools to generate tests, and executing these in the standard verification environment. The added value of these tests is that they exercise true data sharing among processors, are self-checking and resemble commercial multiprocessor code.