PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

CG-Cell: an NPB benchmark implementation on cell broadband engine

Abstract: The NAS Conjugate Gradient (CG) benchmark is an important scientific kernel used to evaluate machine performance and compare characteristics of different programming models. CG represents a computation and communication paradigm for sparse linear algebra, which is common in scientific fields. In this paper, we present the porting, performance optimization and evaluation of CG on Cell Broadband Engine (CBE). CBE, a heterogeneous multi-core processor with SIMD accelerators, is gaining attention and being deployed on supercomputers and high-end server architectures. We take advantages of CBE's particular architecture to optimize the performance of CG. We also quantify these optimizations and assess their impact. In addition, by exploring distributed nature of CBE, we present trade-off between parallelization and serialization, and Cell-specific data scheduling in its memory hierarchy. Our final result shows that the CG-Cell can achieve more than 4 times speedup over the performance of single comparable PowerPC Processor.

Ensuring dependable processor performance: an experience report on pre-silicon performance validation

Abstract: The focus of today's processor validation methodology is primarily on ensuring functional integrity. Increasingly, however, pre-silicon performance validation is becoming part of the design verification challenge. Identification and elimination of performance deficiencies and bugs in the design prior to tape-out is an important aspect of building robust and dependable hardware. Many performance bugs are caused by latent functional defects in the pre-silicon software model of the machine. Besides, robust performance can be a key determinant of quality of service in applications like Web-serving. The authors review the performance validation methodology that they have developed and experimented with over the past few years. They also present examples and experimental results illustrating the use of this methodology in high end PowerPC processor development projects. The scope of the paper is limited to architectural performance, measured by metrics like instructions per cycle (IPC) or its inverse, CPI.

Applying Radiation Hardening by Software to Fast Lossless compression prediction on FPGAs

Abstract: As scientists endeavor to learn more about the world's ecosystems, engineers are pushed to develop more sophisticated instruments. With these advancements comes an increase in the amount of data generated. For satellite based instruments the additional data requires sufficient bandwidth be available to transmit the data. Alternatively, compression algorithms can be employed to reduce the bandwidth requirements. This work is motivated by the proposed HyspIRI mission, which includes two imaging spectrometers measuring from visible to short wave infrared (VSWIR) and thermal infrared (TIR) that saturate the projected bandwidth allocations. We present a novel investigation into the capability of using FPGAs integrated with embedded PowerPC processors to adequately perform the predictor function of the Fast Lossless (FL) compression algorithm for multispectral and hyperspectral imagery. Furthermore, our design includes a multi-PowerPC implementation which incorporates recently developed Radiation Hardening by Software (RHBSW) techniques to provide software-based fault tolerance to commercial FPGA devices. Our results show low performance overhead (4–8%) while achieving a speedup of 1.97× when utilizing both PowerPCs. Finally, the evaluation of the proposed system includes resource utilization, performance metrics, and an analysis of the vulnerability to Single Event Upsets (SEU) through the use of a hardware based fault injector.

Single-Event Upset Mitigation Design Flow for Xilinx FPGA PowerPC Systems

Abstract: Orbital, space-based, and extra-terrestrial applications are susceptible to the effects of high energy charged particles. Single-event upsets (SEUs) can alter the logic state of any static memory element (latch, flip-flop, or RAM cell) including the components of an embedded hard processor. These upsets are unavoidable but correctable for the logic around the processor in FPGA configuration memory. This application note describes mitigation techniques and corresponding design flow when using a Xilinx FPGA with an embedded processor (specifically the PowerPC ® 405 found in the Virtex™-4 FX family) in high-radiation environments. This example contains a block RAM scrubber example for block RAM blocks attached to the processor local bus (PLB) used for code execution. Since this technique cannot triplicate the PowerPC 405 (PPC405), the surrounding logic is mitigated as much as practically possible. Therefore, the user must determine if the system mitigation is sufficient for the target environment. Note: It is essential for the reader to have a basic understanding of the Xilinx tool flow using the Xilinx Platform Studio (XPS), triple-module-redundancy (TMR) techniques, the Xilinx TMRTool, and ISE™ software. An in-depth understanding of [Ref 1] is also essential. In addition, an understanding of VHDL design and practice is recommended.

Self-reconfigurable secure file system for embedded Linux

Abstract: With the growth of the portable electronic devices market, not only the protection of the data for the users but also the security of the designs themselves has grown significantly in importance. A solution is presented where a Linux kernel running on a PowerPC processor included in the Virtex-II Pro FPGA family is upgraded to support hardware acceleration on the ciphering tasks. In this way all the programs running on the PPC that make use of the Linux CryptoAPI can be accelerated by hardware in a transparent way without having the programmer to rewrite the applications. To provide more flexibility, the FPGA's self-reconfiguration capability can be used to reprogram any cryptographic algorithm demanded by the Linux CryptoAPI by just including a new software driver for the operating system, thus allowing the internal configuration access port (ICAP) of the FPGA to manage any cryptographic coprocessor at any time. The approach is validated on a real application using the Linux CryptoAPI: a ciphered file system that stores the system data in a secured way.