PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

An embedded microcontroller for spacecraft applications

Abstract: Originally conceived for fault tolerance control of its associated general purpose processor, the embedded microcontroller (EMC) present in BAE Systems Power PCI Bridge application specific integrated circuit (ASIC) has evolved into a processing workhorse finding applications spanning memory controllers, I/O processors as well as continuing to support the RAD750/spl reg/ PowerPC/spl reg/ processor. Development tools have also evolved from a simple assembler to a full development environment including compiler and simulator integrated with the PowerPC tools supporting the RAD750. This paper describes the evolution of the EMC within the Power PCI Bridge, development of its support tools and some of its applications as both a capable assistant to the RAD750 as well as a standalone processing element. Power and performance improvements are highlighted. Comparison to other processor cores that might be used in space is also shown. Discussion of future enhancements will also be mentioned.

Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic

Abstract: FPGA manufacturers have recently embedded hard core microprocessors in FPGA fabric to improve the processing capabilities of their architectures. We present a study of using the Xilinx Virtex family's embedded PowerPC405 processor. We use a Software Defined Radio (SDR) application as a vehicle for investigating effective communications between the PowerPC405 Processor and the surrounding FPGA fabric. A challenging aspect of developing applications that target the PowerPC is the interfacing of the processor with the surrounding reconfigurable logic. We have implemented a dozen different versions of a Software Defined Radio (SDR) application to exercise the various interfaces that enable communication between the processor and the surrounding FPGA fabric. The implementations differ only in the interfaces used. Our study investigates the use of the On Chip Memory (OCM) interface, the Processor Local Bus (PLB) and the On-chip Processor Bus (OPB).We investigate the best interfaces for different data including instructions, stack, heap and user data. Our results indicate that the performance of the SDR application can be increased by as much as 60 percent just by choosing the interfaces that are most appropriate for the different types of data in the implementation. This demonstrates that the performance of FPGA applications that use the embedded processor are dramatically effected by the mechanisms chosen to enable communication between the processor and its surrounding resources.

KernelFaRer: Replacing Native-Code Idioms with High-Performance Library Calls

Abstract: Well-crafted libraries deliver much higher performance than code generated by sophisticated application programmers using advanced optimizing compilers. When a code pattern for which a well-tuned library implementation exists is found in the source code of an application, the highest performing solution is to replace the pattern with a call to the library. Idiom-recognition solutions in the past either required pattern matching machinery that was outside of the compilation framework or provided a very brittle solution that would fail even for minor variants in the pattern source code. This article introduces Kernel Find & Replacer (KernelFaRer), an idiom recognizer implemented entirely in the existing LLVM compiler framework. The versatility of KernelFaRer is demonstrated by matching and replacing two linear algebra idioms, general matrix-matrix multiplication (GEMM), and symmetric rank-2k update (SYR2K). Both GEMM and SYR2K are used extensively in scientific computation, and GEMM is also a central building block for deep learning and computer graphics algorithms. The idiom recognition in KernelFaRer is much more robust than alternative solutions, has a much lower compilation overhead, and is fully integrated in the broadly used LLVM compilation tools. KernelFaRer replaces existing GEMM and SYR2K idioms with computations performed by BLAS, Eigen, MKL (Intel’s x86), ESSL (IBM’s PowerPC), and BLIS (AMD). Gains in performance that reach 2000× over hand-crafted source code compiled at the highest optimization level demonstrate that replacing application code with library call is a performant solution.

A Device-Controlled Dynamic Configuration Framework Supporting Heterogeneous Resource Management.

Abstract: In this paper, a lightweight autonomous reconfiguration approach is developed for Field Programmable Gate Arrays (FPGAs). Under the Multilayer Runtime Reconfiguration Architecture (MRRA) paradigm, hardware configuration information is read and operated on directly at runtime to provide low overhead dynamic reconfiguration. This enables a standardized set of Application Programming Interfaces (APIs) for uniform access to heterogeneous logic and other resources. A prototype MRRA system is developed for Xilinx Virtex II Pro family of FPGAs to exercise partial reconfiguration capability. The Virtex II Pro On-Chip PowerPC core is used to control these reconfiguration protocols implemented in user logic. These two features make an autonomous reconfiguration system possible, allowing a FPGA to efficiently reconfigure itself under the control of a microprocessor core instantiated within the FPGA fabric.

Thermal management of a C4/CBGA interconnect technology for a high-performance RISC microprocessor: the Motorola PowerPC 620/sup TM/ microprocessor

Abstract: This paper presents various thermal management options for a high-performance RISC microprocessor available for controlled-collapse-chip-connection (C4) die attached to a ceramic-ball-grid-array substrate (CBGA), as they apply to air-cooled systems. Computational-fluid dynamics (CFD) methods are used to solve the conjugate heat transfer problems and a thermal test vehicle mounted to a printed-circuit board was used to validate the models. The internal package's contribution is typically less than 18% of the overall junction-to-ambient temperature rise. Of this 18%, approximately 85% is associated with the thermal paste internally sealed; while, the lid and the silicon chip account for the other 15% (approximately equal). For moderate airflow applications in the 1 to 4 m/s, the PowerPC 620 microprocessor will require a relatively large heat sink, approximately 20 times that of the C4/CBGA package, to maintain its die-junction temperature. The proper selection of a thermal interface material is critical in minimizing the thermal contact resistance between the package and the heat sink. Considering, the low interface pressure, the synthetic grease offers the best performance.