PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

A multi-layer fpga framework supporting autonomous runtime partial reconfiguration

Abstract: Partial reconfiguration is a unique capability provided by several Field Programmable Gate Array (FPGA) vendors recently, which involves altering part of the programmed design within an SRAM-based FPGA at run-time. In this dissertation, a Multilayer Runtime Reconfiguration Architecture (MRRA) is developed, evaluated, and refined based on this technique for Autonomous Runtime Partial Reconfiguration of FPGA devices. Under the proposed MRRA paradigm, FPGA configurations can be manipulated at runtime using on-chip resources. Operations are partitioned into Logic, Translation, and Reconfiguration layers along with a standardized set of Application Programming Interfaces (APIs). At each level, resource details are encapsulated and managed for efficiency and portability during operation. An MRRA mapping theory is developed to link the general logic function and area allocation information to the device related physical configuration level data by using mathematical data structure and physical constraints. In some special certain scenarios, configuration bit stream data can be read and modified directly for fast operations, relying on the use of similar logic functions and common interconnection resources for communication. A corresponding logic control flow is also developed for MRRA to make the entire process autonomous. Several prototype MRRA systems are developed on a Xilinx Virtex II Pro platform. The Virtex II Pro on-chip PowerPC core and block RAM are employed to manage control operations while multiple physical interfaces establish and supplement autonomous reconfiguration capabilities. Area, speed and power optimization techniques are developed based on the developed Xilinx prototype. Evaluations and analysis of these prototype and techniques are performed on a number of benchmark and hashing algorithm case studies. The results indicate that the resource utilization, run-time performance and power consumptions using the developed architecture and approaches all achieve significant improvement compared with Xilinx proposed baseline reconfiguration flow. The Genetic Algorithm (GA) for FPGA fault tolerance is finally tested as an ultimate high-level application running on this architecture. It demonstrated that this is a hardware and software infrastructure that enables an FPGA to dynamically reconfigure itself efficiently under the control of a soft microprocessor core that is instantiated within the FPGA fabric. Such a system combines the benefits of intelligent control, fast reconfiguration and low overhead.

Centralized protection, measurement and control device and realizing method thereof

Abstract: The invention discloses a centralized protection, measurement and control device which comprises the following functional plug-ins: a PowerPC board, a master control PowerPC board, a CPU board, a high-speed serial bus board and a liquid crystal display board, wherein the PowerPC board is arranged on the high-speed serial bus board by plug-in connection, comprises a sampling PowerPC board and receives a sampling packet from a merging unit or sent from the protection, measurement and control device through a sampling network on process level; the master control PowerPC board communicates with abackground and a master controller through the network; the CPU board is arranged on the high-speed serial bus board by plug-in connection and used for realizing the data calculation and the protection function of all intervals; the high-speed serial bus board is an access board for all the plug-ins and used for data transmission among the plug-ins; and the liquid crystal display board is connected with the master control PowerPC board through a built-in network port The device can reduce the complex wiring among all the intervals on the secondary side of a substation and reduce the work of design, manufacture and maintenance of secondary equipment of an automatic system of the substation

Analyzing a PowerPC/sup TM/ 620 microprocessor silicon failure using model checking

Abstract: When silicon is available, newly designed microprocessors ore tested in specially equipped hardware laboratories, where real applications can be run at hardware speeds. However, the large volumes of code being run, plus the limited access to the internal nodes of the chip, make it extraordinarily difficult to characterize the nature of any failures that occur. In this paper, we describe how the formal verification technique of temporal logic model checking was used to quickly characterize a design error exhibited during hardware testing of the PowerPC 620 microprocessor. We claim that model checking can efficiently characterize such failures when certain pre-conditions are met. We also show how the same error could have been revealed early in the design cycle, by model checking a short and simple correctness specification. We discuss the implications of this for verification methodologies over the full design cycle.

A dynamic binary translation approach to architectural simulation

Abstract: We present the design of a PowerPC-based simulation infrastructure for architectural research. Our infrastructure uses an execution-driven out-of-order processor timing simulator from the SimpleScalar tool set. While porting SimpleScalar to the PowerPC architecture, we would like to remain compatible with other versions of SimpleScalar. We accomplish this by performing dynamic binary translation of the PowerPC instruction set architecture to the SimpleScalar instruction set architecture, and by mapping the PowerPC architectural state onto the SimpleScalar register set. Using this infrastructure, we execute unmodified PowerPC binaries on an out-of-order processor timing simulator which implements the SimpleScalar architecture. We describe and investigate trade-offs in the translation of some complex PowerPC instructions and advocate adoption of speculative decode to optimize instruction translations for the common case. We find that simple decode predictors can reach better than 90% accuracy for guiding speculative decode.

Design and development of Modbus/RTU master monitoring system based on embedded PowerPC platform

Abstract: Modbus protocol is widely used in the industrial control field because of its excellent reliability, flexibility, real-time performance etc. It becomes one of the international actuality industrial standards and including lots of industrial equipments using Modbus as their communication protocol such as PLC, DCS, intelligent instruments etc. Embedded system focus on applications, and it can adapt to the strict requirements of functions, reliability, cost, size, power consumption, and so on. PowerPC series processor of Freescale semiconductor CO., LTD is an ideal platform of RISC embedded applications, which has powerful communication ability, system stability and disturb rejection ability. Based on the MPC8248 embedded processor of Freescale, a data acquisition and monitoring platform using Modbus/RTU master protocol based on embedded PowerPC and embedded Linux operating system is designed in this paper, which can realize the functions in industrial fields such as data acquisition, remote monitoring and network communication etc.