Showing papers on "Precision rectifier published in 2020"

A Low Walk Error Analog Front-End Circuit With Intensity Compensation for Direct ToF LiDAR

Abstract: An analog front-end (AFE) circuit comprising an amplifier module, a peak detector, and a timing discriminator has been designed to facilitate the target identification for direct time-of-flight (dToF) LiDAR. The amplitude saturation error (ASE) is compensated in this article for the intensity determination, which is conducted based on the combination of the pulse width and peak detector. Together with the improved walk error compensation scheme, the proposed AFE circuit can attain the distance and intensity information simultaneously with lower cost and larger dynamic range. A specific frequency compensation method is proposed with a shunt feedback TIA, which improves the stability and mitigates the impact of the package parasitics. The measured -3-dB bandwidth, transimpedance gain, and the input-referred noise current are 281 MHz, 86 dB $\Omega $ , and 4.68 pA/ $\surd $ Hz respectively. The proposed AFE circuit, which is fabricated in $0.18~\mu \text{m}$ CMOS technology, achieves the distance accuracy of ±30 ps and the intensity accuracy of ±4% in the dynamic range of 1:5000 without gain control scheme.

A 66-dB Linear Dynamic Range, 100-dB· $\Omega$ Transimpedance Gain TIA With High-Speed PDSH for LiDAR

Abstract: A wide dynamic range (DR) receiver for the linear pulsed light detection and ranging (LiDAR) is presented, including a high linear DR transimpedance amplifier (TIA) with digital codes to vary its gain and a high-speed peak detector sample and hold (PDSH) circuit to capture the peak value of echo pulses. In order to extend the linear DR without reducing the bandwidth, a source follower is introduced to turn the common-gate amplifier into a large swing current mirror amplifier, leading to stable and low input impedance and three programmable transimpedance gain modes. For improving the precision of the PDSH circuit, a variable current source is utilized to replace the rectifying current mirror to alleviate the overshoot and pedestal voltage error. Implemented in 0.18- $\mu \text{m}$ standard CMOS technology, the proposed TIA achieves a high linear DR of 66 dB with a wide bandwidth of 110 MHz, and the highest gain reaches 100 dB· $\Omega $ . The error of PDSH circuit is less than 0.4% for 70-ns peaking width pulses with amplitude from 100 mV to 1.1 V. The receiver chip consumes 21 mW with a single 3.3-V supply, where the TIA and PDSH consume 8 and 13 mW, respectively.

Self-Powered Piezoelectric and Thermoelectric Energy Simultaneous Extraction Interface Circuit Based on Double Stack Resonance

Abstract: A hybrid self-powered synchronous electric charge extraction (HSP-SECE) interface circuit based on double stack resonance is presented in this paper. The proposed HSP-SECE interface circuit can simultaneously extract energy from piezoelectric transducer (PZT) and thermoelectric generator (TEG) when the peak open-circuit voltage of the PZT is detected by passive peak detector. The output power of the proposed interface circuit can reach three times of that of full-bridge rectifier circuit at the maximum power point, and the maximum efficiency of harvesting thermoelectric energy can reach 76% at 200 mV of the open-circuit voltage of the TEG. The simulation and experimental results show the superiority of the HSP-SECE circuit.

Resistorless current mode precision rectifier using EXCCII

Abstract: In this paper, a new current mode precision rectifier circuit is proposed using a single EXCCII and two nMOS transistors. The novelty of the circuit is that it can provide all the possible rectified outputs, namely ± full wave as well as ± half wave simultaneously without any alteration of topology. Moreover, it has low input impedance and high output impedance, which is suitable for fully cascadable operation. It is suitable for a very high frequency of operation. The operating frequency is found to be 125 MHz and above. The temperature, average DC voltage output, noise, power consumption, input dynamic range (± 500 µA), Monte-Carlo and total harmonic distortion analysis are carried out to check the performance quality. The conversion of sinusoidal signal to root-mean-square circuit is also included here as an application of the proposed rectifier The proposed circuit is simulated using Cadence ORCAD PSpice simulator with 0.18 µm CMOS technology parameters. Simulation results agree well with the theoretical analysis.

RF-Rate Hybrid CNN Accelerator Based on Analog-CMOS and Xilinx RFSoC

Abstract: The superior performance of deep learning (DL) has sent shock waves in the machine learning community. The high adoption rate of DL has set new demands on computational throughput, latency, and power efficiency of the computing infrastructure. In addition to conventional approaches to acceleration of the inference component of DL systems based on GPUs, cloud computing, ASIC/FPGAs and custom vector processors (such as tensor processing units), there is renewed interest in high-frequency analog circuits for DL inference. Analog computing is a potential candidate for meeting challenging requirements in throughput, latency and power efficiency. Because DL inference has superior noise resilience and relatively low accuracy needs (typically less than 8 bits), analog circuits can provide a promising alternative to all-digital accelerators. This paper presents early work on the design of an analog CMOS accelerator that performs analog convolution and decision operations in parallel and in real-time by pairing a high-frequency operational amplifier-based CNN filtering kernel with a rectified linear unit (ReLu) non-linearity based on an active precision rectifier circuit. The analog accelerator was designed in a 45 nm CMOS process and simulated in Cadence Spectre. Image convolution results are presented and compared with MATLAB simulations. The proposed solution also employs Xilinx RF System-on-Chip (SoC) devices based on the Xilinx ZCU1285 RFSoC platform to interface digital inputs and outputs with the proposed RF-rate analog inference accelerator.

A 2.4 GHz 2.9 mW Zigbee RF Receiver with Current-Reusing and Function-Reused Mixing Techniques

Abstract: This study presents a low-power Zigbee receiver with a current-reusing structure and function-reused mixing techniques. To reduce the overall power consumption, a low noise amplifier (LNA) and a power amplifier (PA) share the biasing current with a voltage-controlled oscillator (VCO) in the receiving (RX) mode and transmitting (TX) mode, respectively. The function-reused mixer reuses the radio frequency trans-conductance (RF gm) stage to amplify the down-converted intermediate frequency (IF) signal, obtaining a free IF gain without extra power consumption. A peak detector circuit detects the receiving signal strength and auto-adjusts the biasing current to save power when a strong signal strength is detected. Meanwhile, the peak detector helps to provide a coarse gain control as part of the auto-gain-control function. As part of the IF gain range is shared by the multiple-feedback (MFB) low-pass filter, the number of programmable-gain IF amplifier stages can be reduced, which also means a decrease in power consumption. A prototype of this wireless sensor network (WSN) receiver was designed and fabricated using the TSMC 130 nm CMOS process under a supply voltage of 1 V. The entire receiver realizes a noise figure (NF) of 3.5 dB and a receiving sensitivity of −90 dBm for the 0.25 Mbps offset quadrature phase shift keying (O-QPSK) signal with a power consumption of 2.9 mW.

A Current-mode ACG base on Sub-threshold MOS Translinear Principle

Abstract: This paper presents a current mode of automatic gain control (AGC). The proposed AGC is designed based on the principle of sub-threshold MOS translinear. It consists of a current-mode exponential amplifier, a precision rectifier, a low pass filter, and an integrator. The AGC’s performance is demonstrated by PSPICE simulations in 0.18 $\mu m$ TSMC CMOS technology. The simulation results of the proposed circuit at the supply voltage of ± 1.2V show that the settling time is 4ms and the maximum power consumption is 1.27mW

Power supply for voltage controlled oscillators with automatic gain control

Abstract: The disclosure relates to technology for power supply for a voltage controller oscillator (VCO). A peak detector circuit determines the amplitude of the output for the VCO, which is compared to a reference value in an automatic gain control loop. An input voltage for the VCO is determined based on a difference between the reference value and the output of the peak detector circuit. The peak detector circuit can be implemented using parasitic bipolar devices in an integrated circuit formed in a CMOS process.

A Low Power 60 GHz 6 V CMOS Peak Detector

Abstract: A low-power, compact mm-Wave voltage peak detector capable to withstand input voltage levels up to 6 V is presented. The circuit is realized in a 22 nm fully depleted silicon on insulator (FD-SOI) CMOS technology and employs 1.8 V I/O transistors and use a clamping scheme to increase its operating voltage range, both of which are novel approaches. The circuit operation is verified up to 67 GHz. A 3-dB amplitude demodulation bandwidth of 10 MHz at a 61.25 GHz carrier frequency was measured while the detector consumed only 6 µW power from a supply voltage of 1.8 V. The proposed peak detector has an active area of 35 µm × 40 µm including the bypass and output capacitors completely below the patterned ground plane of a transmission line, and thus it does not consume any additional silicon area.

CMOS Analog AGC for Biomedical Applications

Abstract: In this paper, we present the design of an analog Automatic Gain Control with a small silicon area and reduced power consumption using a 0.5 μ m process. The design uses a classical approach implementing the AGC system with simple blocks, such as: peak detector, difference amplifier, four-quadrant multiplier, and inversor amplifier. Those blocks were realized by using a modified Miller type OPAMP, which allows indirect compensation, while the peak detector uses a MOS diode. The AGC design is simulated using the Tanner-Eda environment and Berkeley models BSIM49 of the On-Semiconductor C5 process, and it was fabricated through the MOSIS prototyping service. The AGC system has an operation frequency of around 1 kHz, covering the range of biomedical applications, power consumption of 200 μ W, and the design occupies a silicon area of approximately 508.8 μ m × 317.7 μ m. According to the characteristics obtained at the experimental level (attack and release time), this AGC can be applied to hearing aid systems.

Dual mode power supply for voltage controlled oscillators

Abstract: The disclosure relates to technology for power supply for a voltage controller oscillator (VCO), where the power supply has a closed loop mode and an open loop mode. In closed loop mode, a peak detector circuit determines the amplitude of the output for the VCO, which is compared to a reference value in an automatic gain control loop. An input voltage for the VCO is determined based on a difference between the reference value and the output of the peak detector circuit. The peak detector circuit can be implemented using parasitic bipolar devices in an integrated circuit formed in a CMOS process. While operating in the closed loop mode, a controller monitors the input voltage and, when the input voltage is stabilized, the controller uses this input voltage value determined in open loop mode.

Precision Full-Wave Rectifier - Practical Realization in Discrete Technology

Abstract: Practical realization of the full-wave precision rectifier in discrete technology is presented in this paper. Bipolar transistors with discrete elements on the raster board where used for the realization of the full-wave precision rectifier. To verify the proposed design of the full-wave precision rectifier PSPICE program was used. Simulation results are demonstrated and likened with the results of the measurement of the realization that was published.

Current peak sensor for pulsed laser diode array

Abstract: An apparatus and method for current peak detection. The apparatus includes a pulse laser diode array, a sense resistor, a capacitive voltage divider (CVD) electrically coupled to the pulse laser diode array, a first current rectifier, a second current rectifier, a first current peak detector, a second current peak detector, an analog-to-digital converter (ADC) operable to convert the analog outputs from each current peak detector to a digital output signal, and a digital signal processing (DSP) unit operable to detect, from the digital output signal, a current peak pulse at the top and the bottom of the sense resistor.

Digitally-Assisted Peak Detector for Periodic Signal

Abstract: A high-precision digitally-assisted peak detector (PD) circuit is presented. While conventional analog PD circuits suffer from Process, Voltage, and Temperature (PVT) variation, as well as noise and device mismatch, resolution of the proposed PD is only limited by quantization noise of the digital tracking circuit. At startup, a binary search algorithm is employed to quickly find the signal amplitude. After an initial phase, the proposed digitally assisted PD switches to tracking mode in order to follow the peak of the input signal. Designed for periodic systems, such as Voltage Controlled Oscillators (VCOs) and Amplitude Modulation (AM) detectors, the proposed digitally assisted PD exhibits a total of 2 mVpkpk error. The proposed PD shows very low sensitivity to noise of the analog circuitry due to digital averaging. Moreover, calibration mechanisms have been proposed to detect and remove the offset of comparator circuits. In 0.18µm technology, the implemented peak detector consumes 438.5nW power in the analog section and the digital calibration part consumes 28.52µW.

Intelligent device for measuring distance to point of damage of power transmission lines

Abstract: FIELD: measuring equipment.SUBSTANCE: invention relates to measuring equipment and can be used in production of devices for automatic distance estimation to the accident site in transmission lines. Essence: an information signal parameter stabilization unit comprising an information signal amplifier with two negative feedback loops. First noise stabilization circuit is made in form of serial circuit connected to amplifier output signal from peak detector connected by common point to positive power bus, and an amplifier connected through a resistor to the input of the information signal amplifier. Second circuit for stabilizing the amplitude of the information signal is in form of a series circuit of a peak detector connected by a common point to a null power bus, and by an output to an inverting input of the differential amplifier. Potentiometer performing the function of setting device is connected to non-inverting input of differential amplifier. Output of the differential amplifier is connected to an optron connected to the feedback circuit of the information signal amplifier, which controls the amplification factor. Output of the amplifier is connected to the input of the pulse former, the output of which is connected to the "0" input of the trigger, the "1" input of which is connected to the generator of rectangular pulses. Trigger output is connected to the first input of the switch, and the second input is connected to the clock pulse generator. Output of the key is connected to the input of the pulse counter, the output of which is connected to the first input of the adder, to the second input of which the first output of the microcontroller is connected.EFFECT: high-speed operation and reliability of the device.1 cl, 4 dwg

An electronic device including a harvest circuit being input aperiodic signal

Abstract: Provided is an electronic device which can improve driving efficiency of a power stage. The electronic device comprises a harvest circuit. The harvest circuit includes: a power stage block including at least one MOSFET; and a control block including a wakeup control block and controlling the at least one MOSFET. The wakeup control block includes: a current starved inverter circuit using a signal which aperiodically occurs as an input and limiting current sinking and current supply of an inverter; and an adaptable biasing inverter circuit using an output of the current starved inverter circuit as an input and outputting a signal for controlling a voltage peak detector constituting the control block.

Automatic gain control for passive optical network

Abstract: An automatic gain control circuit controls a gain of a burst mode amplifier. A peak detector includes an input coupled to an output of the amplifier. A plurality of resistors is coupled in series between an input of the first amplifier and the output of the first amplifier for setting the gain of the amplifier. A first gain stage is responsive to an output signal of the peak detector for disabling a first resistor of the plurality of resistors to alter the gain of the first amplifier. A second gain stage is responsive to the output signal of the peak detector for disabling a second resistor of the plurality of resistors to alter the gain of the first amplifier. A comparator responsive to the output signal of the peak detector causes a pulse generator to enable the first gain stage and second gain stage each burst mode.