Showing papers on "Precision rectifier published in 2021"

Precision rectifier circuit using current-mode approach and grounded resistors

Abstract: This article is devoted to a new circuit proposal for precision rectification, which is designed using current feedback operational amplifiers The new proposed circuit operation is clearly discuss

Voltage mode ASK/BPSK modulator, its extended applications in precision rectifier and data communication using DXCCII

Abstract: In this paper, two new modulator circuits are presented to realize two types of digital modulations, namely amplitude shift keying (ASK) and Binary phase shift keying (BPSK). The modulator circuits use one dual-X second-generation current conveyor (DXCCII), three MOS transistors, and one or two resistors. Since in data communication, there is a need for a demodulator and a modulator, a basic demodulator as an application of ASK modulator is presented using a rectifier, envelope detector, and comparator. Moreover, in an integrated circuit (IC), the modularity of sub-circuit is preferred, especially for the ease of fabrication. In maintaining the modularity, an attempt is made to design a precision rectifier, needed for demodulator, as an extension of the proposed modulator with little modifications. The proposed modulators possess the following important features: use all grounded passive components, ASK and BPSK obtain simultaneously, no need for matching passive components, circuits are fully cascadable and easily extendable to a precision rectifier. A non-ideal analysis is carried out. The proposed circuits are verified by PSPICE simulation with a supply voltage of ±0.9 V in 0.13 µm CMOS TSMC technology. Simulation results corroborate the theoretical proposition. Furthermore, the proposed ASK and BPSK modulator circuit is experimentally verified.

A mV-level real-time peak-voltage detection circuit based on differential structure.

Abstract: A peak-voltage detection circuit based on a differential comparison structure is proposed to synchronize the control and the input signal. The detection circuit is hence free of reset signals for the sampling capacitors. Furthermore, a two-channel parallel sample and hold structure (i.e., S/H circuit) is used, and a correlated double sampling technique is used, in combination with the ping-pong technique, to sample the signal value and offset voltage within one sample cycle. Consequently, the parallel connected S/H structure can not only extract the offset voltage of the op-amp but also effectively reduce the detection error, which is caused by circuit noise and leakage current. Measurements of the implemented peak detector show that in the case that the detection signal frequency is 20 kHz and the amplitude is 10 mV, the detection error is decreased to 30 µV with the equivalent output noise of 71 nV/Hz.

Electronically Tunable Full Wave Precision Rectifier Using DVCCTAs

Abstract: This work presents a voltage mode scheme of a full-wave precision rectifier circuit using an analog building block differential voltage current conveyor transconductance amplifier (DVCCTA) including five NMOS transistors. The proposed design is essentially suited for low voltage and high-frequency input signals. The operation of the proposed rectifier design depends upon the region of operation of NMOS transistors. The output waveform of the presented rectifier design can be made electronically tunable by controlling the bias voltage. The functional correctness and verification of the presented design are performed using 0.25-µm TSMC technology under the supply voltage of ±1.5 V. The absence of a resistor leads to a minimal parasitic effect. To obtain further insight on the robustness of the circuit, a Monte Carlo simulation and corner analysis are also presented. The circuit is verified experimentally by incorporating a breadboard model with the help of commercially available ICs CA3080 (operational transconductance amplifier) and AD844AN (current feedback operational amplifier) and offers remarkable compliance with both theoretical and simulation outcomes. The presented design has been laid out on Cadence virtuoso, which consumes a chip area of 9044 µm2.

Broadband CMOS RF Logarithmic Power Detector for sub-6 GHz 5G Applications

Abstract: This paper describes the design of an RF power detector which has broad bandwidth and high dynamic range. The proposed RF power detector includes a low noise amplifier (LNA), limiting amplifiers, a peak detector and an adder circuit. The amplifier circuits uses cascode structure and inductive shunt peaking to achieve wide operating frequency range with band pass matching network for matching the RF input to 50Ω. Designed using UMC 180nm RFCMOS, the power detector circuit provides a largely linear relation between input logarithmic power and output DC voltage for the frequency range from 300 MHz to 5.4 GHz. The percentage bandwidth is 178.94%. The RF power detector circuit is tested for input power ranging from −70dBm to 0 dBm. The circuit exhibits dynamic range of 50 dB from 300 MHz to 5.4GHz and 70 dB from 700MHz to 4 GHz. This makes RF power detector suitable for broadband use in the sub-6 GHz 5G applications.