Precision Time Protocol

About: Precision Time Protocol is a research topic. Over the lifetime, 604 publications have been published within this topic receiving 6006 citations. The topic is also known as: PTP & IEEE 1588.

A simulation framework for IEEE 1588

Abstract: IEEE 1588 specifies the Precision Time Protocol (PTP). The design space for PTP implementations is large, and system designers have to make trade-offs. A sophisticated and extensible simulation tool can assist PTP system designers when exploring the design space. This paper serves as an introduction to LibPTP, which is an OMNeT++-based simulation framework for PTP networks. LibPTP facilitates building PTP networks using Ordinary, Boundary, and Transparent clocks. For instance, it enables designers to study different configuration options, to compare delay mechanisms, or switch between clock servos. The paper gives an overview of the current feature set of LibPTP, and demonstrates LibPTP's capabilities through exemplary experiments. The demonstrations encompass analyzing the choice of synchronization intervals, the impact of path asymmetry, and daisy chaining of clocks.

Hardware Assisted Clock Synchronization with the IEEE 1588-2008 Precision Time Protocol

Abstract: Emerging technologies such as Fog Computing and Industrial Internet-of-Things have identified the IEEE 802.1Q amendment for Time-Sensitive Networking (TSN) as the standard for time-predictable networking. TSN is based on the IEEE 1588-2008 Precision Time Protocol (PTP) to provide a global notion of time over the local area network. Commonly, off-the-shelf systems implement the PTP in software where it has been shown to achieve microsecond accuracy. In the context of Fog Computing, it is hypothesized that future industrial systems will be equipped with FPGAs. Leveraging their inherent flexibility, the required PTP mechanisms can be implemented with minimal hardware usage and can achieve comparable synchronization results without the need for a PTP-capable transceiver. This paper investigates the practical challenges of implementing the PTP and proposes a hardware architecture that combines hardware-based timestamping with a rate adjustable clock design. The proposed architecture is integrated with the Patmos processor and evaluated on an experimental setup composed of two FPGA boards communicating through a commercial-off-the-shelf switch. The proposed implementation achieves sub-microsecond clock synchronization with a worst-case offset of 138 ns.

Synchrophasors measurement in a GPS-IEEE 1588 hybrid system

Abstract: This paper presents a study on a hybrid architecture considering Global Positioning System (GPS) and Precision Time Protocol (PTP), defined in Standard IEEE 1588, for applications in electric power systems, with reference to one of the most challenging measurement problems, namely the measurement of synchrophasors. The proposed approach refers in particular to situations in which many measurement devices, connected to each other by suitable communication links, are located in a geographically limited subarea of the power system. A laboratory experimental setup has been built to evaluate the performance achievable with this solution. A detailed analysis of the obtained results is presented. Copyright © 2010 John Wiley & Sons, Ltd.

Method and device for time synchronization convergence based on precision time protocol

Abstract: The invention discloses a method and a device for time synchronization convergence based on the precision time protocol. The method comprises the followings steps of: interacting a synchronization message with a grandmaster clock node at each passive port by a slave clock node, performing time synchronization calculation, and establishing and maintaining the alternative time information corresponding to the passive port according to a result of the time synchronization calculation; when the slave clock node detects that an upstream clock synchronization network of a slave port or any passive port undergoes topology change, triggering BMC (Best Master Clock) computation, determining a port with the optimal clock priority information according to a BMC computation result, if the port with the optimal clock priority information is a passive port, switching the passive port into a slave port, and performing time synchronization processing on a local clock according to the alternative time information corresponding to the passive port. With the method and the device, the out-of-step time of the slave clock node can be reduced during the topology change of the network.

Method for improving accuracy in computation of one-way transfer time for network time synchronization

Abstract: A method for improving accuracy in the computation of a one-way transfer time between two networked devices. In one aspect, variability in time transfer latency that is caused by cache loading, data structure setup time, and scheduling variability in software is reduced by initiating a first sequence of loading data structures into cache and priming scheduling, and then initiating a second sequence of calibrating the timing of a subsequent synchronization message so that the completion of the first sequence occurs just in time for the reception of the synchronization message. The method is applicable for any network time synchronization protocol, including Network Time Protocol (NTP) and Precision Time Protocol (PTP).