Showing papers on "Prime-factor FFT algorithm published in 2018"

A nonuniform fast Fourier transform based on low rank approximation

Abstract: By viewing the nonuniform discrete Fourier transform (NUDFT) as a perturbed version of a uniform discrete Fourier transform, we propose a fast and quasi-optimal algorithm for computing the NUDFT based on the fast Fourier transform (FFT). Our key observation is that an NUDFT and DFT matrix divided entry by entry is often well approximated by a low rank matrix, allowing us to express a NUDFT matrix as a sum of diagonally scaled DFT matrices. Our algorithm is simple to implement, automatically adapts to any working precision, and is competitive with state-of-the-art algorithms. In the fully uniform case, our algorithm is essentially the FFT. We also describe quasi-optimal algorithms for the inverse NUDFT and two-dimensional NUDFTs.

Feedforward FFT Hardware Architectures Based on Rotator Allocation

Abstract: In this paper, we present new feedforward FFT hardware architectures based on rotator allocation. The rotator allocation approach consists in distributing the rotations of the FFT in such a way that the number of edges in the FFT that need rotators and the complexity of the rotators are reduced. Radix-2 and radix-2 k feedforward architectures based on rotator allocation are presented in this paper. Experimental results show that the proposed architectures reduce the hardware cost significantly with respect to previous FFT architectures.

High-speed channel equalization scheme for 100 Gbps system

Abstract: In the terahertz frequency range, there is an abundance of bandwidth (25GHz ∼ 50 GHz) available to achieve ultra-high-speed wireless communication and enabling data rates up to 100 Gbps. We choose Parallel Sequence Spread Spectrum (PSSS) as an analog friendly modulation and coding scheme that allows for an efficient mixed-signal implementation of a 100 Gbps wireless communication system. We have completed measurements using a 240 GHz RF Millilink front end combined with PSSS as baseband modulation scheme and evaluated channel estimates. In this paper, a high-speed channel equalization algorithm was designed and implemented on an FPGA as well as an ASIC. One of the main operations in performing channel equalization is to evaluate discrete Fourier transform (DFT) of channel estimates. This work also examines the multidimensional DFT decomposition theory which is the transformation of a one dimensional DFT into two-dimensional DFT, whereby the index mapping is done using the Chinese remainder theorem. We have modified the prime factor algorithm (PFA) to perform a complex DFT on channel estimate samples. PFA decomposes a long transform DFT into several short transforms DFTs which are carried out using a minimal amount of multiplications. By skipping the cumbersome process of evaluating twiddle factors, the result is a very suitable architecture for high-speed design. We have designed and implemented a high-speed channel equalization on a Vitrex Ultrascale FPGA running at 166.67 MHz with a low latency of only one clock cycle. We have also synthesized our design using the Synopsis DC Ultra tool with 40 nm NanGate open cell libraries. The design required 0.28 mm2 area, 21 mW power and operates on a clock frequency of 158 MHz.

An all-optical soliton FFT computational arrangement in the 3NLSE-domain

Abstract: In this paper an all-optical soliton method for calculating the Fast Fourier Transform (FFT) algorithm is presented. The method comes as an extension of the calculation methods (soliton gates) as they become possible in the cubic non-linear Schrodinger equation (3NLSE) domain, and provides a further proof of the computational abilities of the scheme. The method involves collisions entirely between first order solitons in optical fibers whose propagation evolution is described by the 3NLSE. The main building block of the arrangement is the half-adder processor. Expanding around the half-adder processor, the "butterfly" calculation process is demonstrated using first order solitons, leading eventually to the realisation of an equivalent to a full Radix-2 FFT calculation algorithm.

Sparse fast Fourier transform for exactly sparse signals and signals with additive Gaussian noise

Abstract: In recent years, the Fourier domain representation of sparse signals has been very attractive. Sparse fast Fourier transform (or sparse FFT) is a new technique which computes the Fourier transform in a compressed way, using only a subset of the input data. Sparse FFT computes the desired transform in sublinear time, which means in an amount of time that is smaller than the size of data. In big data problems and medical imaging to reduce the time that patient spends in MRI machine, FFT algorithm is not ‘fast’ enough anymore; therefore, the concept of sparse FFT is very important. Similar to compressed sensing, sparse FFT algorithm computes just the important components in the frequency domain in sublinear time. In this work, sparse FFT algorithm is studied and implemented on MATLAB and its performance is compared with Ann Arbor FFT. A filter is used to hash the frequencies in the n dimensional frequency-sparse signal into B bins, where $$B=n/16$$ . The filter is used for analyzing an important fraction of the whole signal, and therefore, instead of computing n point FFT, B point FFT is computed, and this results in a faster Fourier transform. The probability of success of the implemented algorithm is investigated for noiseless and noisy signals. It is deduced that as the sparsity increases, the probability of perfect transform also increases. If the performances of the algorithm in both cases are compared, it is clearly seen that the performances degrade when there is noise. Therefore, it can be concluded that the algorithm should be improved especially for noisy considerations. The solvability boundary for a constant probability of error is deducted and added to give insight for future studies.

Characteristic Analysis of 1024-Point Quantized Radix-2 FFT/IFFT Processor

Abstract: The precise analysis and accurate measurement of harmonic provides a reliable scientific industrial application However, the high-performance DSP processor is the important method of electrical harmonic analysis Hence, in this research work, the effort was taken to design a novel high-resolution single 1024-point fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) processors for improvement of the harmonic measurement techniques Meanwhile, the project is started with design and simulation to demonstrate the benefit that is achieved by the proposed 1024-point FFT/IFFT processor The pipelined structure is incorporated in order to enhance the system efficiency As such, a pipelined architecture was proposed to statically scale the resolution of the processor to suite adequate trade-off constraints The proposed FFT makes use of programmable fixed-point/floating-point to realize higher precision FFT

A Prime-Factor Algorithm for the Inverse Discrete Sine Transform and its Architecture

Abstract: In this paper, we have suggested a simple scheme for prime-factor decomposition of Inverse Discrete Sine Transform (IDST) and systolic mesh architecture for its efficient implementation. In the systolic architecture the transposition of the intermediate matrix is avoided in this structure by orthogonal processing during the pair of matrix multiplication i.e., if the processing for the first matrix multiplication takes place along X-direction, the processing for the second matrix multiplication is carried out along Y-direction. Due to this feature, the systolic architecture is highly compact, offers saving for transposition hardware and at the same time yields high throughput with less latency. The proposed systolic architecture has very less area complexity, less computation time and very high VLSI performance measures compared with existing structures. Due to orthogonal nature of the Discrete Sine Transform (DST), the forward transform may however be realized by the transpositions of the inverse transform.