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Prime-factor FFT algorithm

About: Prime-factor FFT algorithm is a research topic. Over the lifetime, 2346 publications have been published within this topic receiving 65147 citations. The topic is also known as: Prime Factor Algorithm.


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Book ChapterDOI
21 Aug 1989
TL;DR: This paper reports an explanation of an intricate algorithm in the terms of a potentially mechanisable rigorous-development method, using notations and techniques of Sheeran and Bird and Meertens and claiming that these techniques are applicable to digital signal processing circuits.
Abstract: This paper reports an explanation of an intricate algorithm in the terms of a potentially mechanisable rigorous-development method. It uses notations and techniques of Sheeran [1] and Bird and Meertens [2, 3]. We have claimed that these techniques are applicable to digital signal processing circuits, and have previously applied them to regular array circuits [4, 5, 6].

10 citations

Journal ArticleDOI
TL;DR: Analysis of the numbers of complex additions and multiplications required indicate that implementations of the radix-4 row-column FFT and 4 × 4 vector radix FFT on the same minicomputer would run slower than the multiple vector implementation.
Abstract: A new version of the radix-2 row-column method for computing two-dimensional fast Fourier transforms is proposed. It uses a ``multiple vector'' FFT algorithm to compute the transforms of all the columns in an array simultaneously while avoiding all trivial multiplications. The minicomputer implementation of the algorithm runs faster than the 2 × 2 vector radix FFT algorithm. Analysis of the numbers of complex additions and multiplications required indicate that implementations of the radix-4 row-column FFT and 4 × 4 vector radix FFT on the same minicomputer would run slower than the multiple vector implementation.

10 citations

Proceedings ArticleDOI
07 Aug 2002
TL;DR: Design results show that the ML-FFT offers flexible tradeoff between arithmetic complexity and numerical accuracy in approximating the DFT, and uses the polynomial transformation to obtain similar multiplier-less approximation of 2D FFT.
Abstract: This paper proposes a new multiplier-less approximation of the 1D discrete Fourier transform (DFT) called the multiplierless fast Fourier transform-like (ML-FFT) transformation. It parameterizes the twiddle factors in conventional radix-2/sup n/ or split-radix FFT algorithms as certain rotation-like matrices and approximates the associated parameters using the sum-of-powers-of-two (SOPOT) or canonical signed digits (CSD) representations. The ML-FFT converges to the DFT when the number of SOPOT terms used increases and has an arithmetic complexity of O(Nlog/sub 2/ N) additions, where N=2/sup m/ is the transform length. Design results show that the ML-FFT offers flexible tradeoff between arithmetic complexity and numerical accuracy in approximating the DFT. Using the polynomial transformation, similar multiplier-less approximation of 2D FFT is also obtained.

10 citations

Book ChapterDOI
27 Aug 2002
TL;DR: A blocking algorithm for a parallel one-dimensional fast Fourier transform (FFT) on clusters of PCs based on the six-step FFT algorithm, which achieves performance of over 1.3 GFLOPS on an 8-node dual Pentium III 1 GHz PC SMP cluster.
Abstract: In this paper, we propose a blocking algorithm for a parallel one-dimensional fast Fourier transform (FFT) on clusters of PCs. Our proposed parallel FFT algorithm is based on the six-step FFT algorithm. The six-step FFT algorithm can be altered into a block nine-step FFT algorithm to reduce the number of cache misses. The block nine-step FFT algorithm improves performance by utilizing the cache memory effectively. We use the block nine-step FFT algorithm to design the parallel one-dimensional FFT algorithm. In our proposed parallel FFT algorithm, since we use cyclic distribution, all-to-all communication is required only once. Moreover, the input data and output data are both can be given in natural order. We successfully achieved performance of over 1.3 GFLOPS on an 8-node dual Pentium III 1 GHz PC SMP cluster.

10 citations

Journal ArticleDOI
R. Trider1
TL;DR: The design for a convolution processor is presented, which employs a single highly parallel implementation of the fast Fourier transform (FFT) algorithm, eminently suited for real-time matched filtering of coded signals encountered in sonar systems.
Abstract: The design for a convolution processor is presented, which employs a single highly parallel implementation of the fast Fourier transform (FFT) algorithm. This processor is eminently suited for real-time matched filtering of coded signals encountered in sonar systems. Computer simulations have shown that this processor, which uses fixed point arithmetic and modest word sizes, can efficiently handle signals with multiple targets and relatively large Doppler shifts. The parallel architecture provides a throughput rate sufficient for computing both forward and inverse transforms in the one processor. The system is flexible permitting frequency domain adaptive beam-forming, attractive in many sonar applications.

10 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20235
202224
20211
20188
201757
201692