Topic
Prime-factor FFT algorithm
About: Prime-factor FFT algorithm is a research topic. Over the lifetime, 2346 publications have been published within this topic receiving 65147 citations. The topic is also known as: Prime Factor Algorithm.
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20 Jul 2001TL;DR: In this article, a semi-variogram is generated by taking the Fourier Transform of the spatial data in the space domain and computing the complex conjugate of FFT (FFT*), complex multiplying FFT and FFT* to produce a complex product, taking the inverse Fourier transform of the complex product to generate a space domain representation of complex product (IFFT), and subtracting IFFT from the zero lag covariance.
Abstract: A Semi-Variogram is generated by taking the Fourier Transform of ‘spatial data in the space domain’ thereby producing a frequency domain representation of the spatial data having a DC component (equivalent to a mean of the spatial data), removing the DC component to produce the frequency domain representation of the spatial data with zero mean (FFT), computing the complex conjugate of FFT (FFT*), complex multiplying FFT and FFT* to produce a complex product, taking the inverse Fourier Transform of the complex product to produce a space domain representation of the complex product (IFFT), and subtracting IFFT from the zero lag covariance to generate a Semi-Variogram. This Abstract is given for the sole purpose of allowing a patent searcher to easily determine the content of the disclosure in this specification.
10 citations
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TL;DR: An algorithm is developed for making magnetic field “reduction-to-the-pole” computations using two-dimensional Fourier series using a “look-up table” to reduce the number of trigonometric functions to be evaluated.
10 citations
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03 Mar 1975TL;DR: In this paper, two kinds of apparatus for combining N 2 chirp-Z transform (CZT) modu of length n 1 to perform a discrete Fourier transform (DFT) of length N 1 N 2.
Abstract: Two kinds of apparatus for combining N 2 chirp-Z transform (CZT) modu of length N 1 to perform a discrete Fourier transform (DFT) of length N 1 N 2 . The first method uses an auxiliary parallel-input, parallel-output, DFT device of size N 2 and allows the transform of size N 1 N 2 to be performed in the same time as is required for a single CZT module to perform a size N 1 transform. The second method uses an auxiliary parallel-input, serial-output, DFT device of size N 2 . If the second method is implemented entirely in a single technology, such as with charge-coupled devices (CCDs), it performs the size N 1 N 2 transform in N 2 times the amount of time required for a single CZT module to perform a size N 1 transform. If N 2 is a composite number, say N 2 = M 1 M 2 , the second method also permits the same hardware to perform M 1 simultaneous transforms of length N 1 M 2 .
10 citations
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08 May 2014
TL;DR: A highly efficient pipelined folded FFT architecture for 8 point R2 FFT is presented here and shows efficiency both in speed and area consumption.
Abstract: Fast Fourier Transforms have become an integral part of any digital communication system and a wide variety of approaches have been tried in order to optimize the algorithm for a variety of parameters, primarily being memory and speed. Major problem in FFT calculation is the increased number of complex multiplication units. Folding transformations are used to design FFT architectures with reduced number of functional units. In the folding transformation, many butterflies in the same column can be mapped to one butterfly unit. A highly efficient pipelined folded FFT architecture for 8 point R2 FFT is presented here. When compared with the normal R2 FFT architecture, the pipelined architecture shows efficiency both in speed and area consumption. Futher reduction in the area can be obtained by using COordinate Rotation for DIgital Computer (CORDIC) algorithm, which is an add and shift algorithm that replaces complex twiddle factor multiplication. The FFT block is designed to be capable of computing 8 point FFT and employs R2 (Radix2) architecture which is simple, elegant and best suited for communication applications. VHDL coding is simulated and synthesized in Xilinx ISE Design Suite 12.1.
10 citations
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12 Mar 2012
TL;DR: A new parallel FFT architecture which combines the split-radix algorithm with a constant geometry interconnect structure which achieves 46% lower power than a parallel radix-4 design at 4.5GS/s when computing a 128-point real-valued transform.
Abstract: High performance hardware FFTs have numerous applications in instrumentation and communication systems. This paper describes a new parallel FFT architecture which combines the split-radix algorithm with a constant geometry interconnect structure. The split-radix algorithm is known to have lower multiplicative complexity than both radix-2 and radix-4 algorithms. However, it conventionally involves an "L-shaped" butterfly datapath whose irregular shape has uneven latencies and makes scheduling difficult. This work proposes a split-radix datapath that avoids the L-shape. With this, the split-radix algorithm can be mapped onto a constant geometry interconnect structure in which the wiring in each FFT stage is identical, resulting in low multiplexing overhead. Further, we exploit the lower arithmetic complexity of split-radix to lower dynamic power, by gating the multipliers during trivial multiplications. The proposed FFT achieves 46% lower power than a parallel radix-4 design at 4.5GS/s when computing a 128-point real-valued transform.
10 citations