Prime-factor FFT algorithm

About: Prime-factor FFT algorithm is a research topic. Over the lifetime, 2346 publications have been published within this topic receiving 65147 citations. The topic is also known as: Prime Factor Algorithm.

Algorithm 545: An Optimized Mass Storage FFT [C6]

Abstract: The program is an implementation of the optimal sorting algorithm of the author [8] which allows a base-2 version of the Cooley-Tukey FFT algorithm [2-4] efficient access to a mass store array. Optimal sorting for the mass storage FFT has been determined independently by DeLotto and Dotti [5, 6], but in the author's version the emphasis is on \"in-place\" array modification. This results in slightly higher mass store I /O than the minimum, but requires no additional mass store working space. The method is a logical extension of the work of Singleton [9] and Brenner [1]. The program computes in place the discrete Fourier transform of a onedimensional or a multidimensional array. In the one-dimensional case the transform is defined by

Accelerating Discrete Fourier Transforms with dot-product engine

Abstract: Discrete Fourier Transforms (DFT) are extremely useful in signal processing. Usually they are computed with the Fast Fourier Transform (FFT) method as it reduces the computing complexity from O(N2) to O(Nlog(N)). However, FFT is still not powerful enough for many real-time tasks which have stringent requirements on throughput, energy efficiency and cost, such as Internet of Things (IoT). In this paper, we present a solution of computing DFT using the dot-product engine (DPE) - a one transistor one memristor (1T1M) crossbar array with hybrid peripheral circuit support. With this solution, the computing complexity is further reduced to a constant O(λ) independent of the input data size, where λ is the timing ratio of one DPE operation comparing to one real multiplication operation in digital systems.

Reduced FFT algorithm for network voltage disturbances detection

Abstract: The paper describes Reduced Fast Fourier Transformation (RFFT), an algorithm of harmonic estimation based on the FFT, created by authors, convenient for voltage dips detection. The algorithm is simple, fast, computationally inexpensive and sufficiently accurate. It is tested in Matlab / SimPowerSystems environment. Results show that the algorithm is faster and better than the FFT, which is advantage in applications for network voltage disturbances detection.

Efficient FFT algorithms for DSP processors using tensor product decompositions

Abstract: A new class of FFT (fast Fourier transform) algorithms that run very efficiently on digital signal processors (DSPs) is described. The algorithms are based on a tensor product factorization of the DFT (discrete Fourier transform). The tensor product factorization not only controls the breakdown into short-length DFTs but also shows the data flow between the various blocks. This allows a better scheduling of operations, which again gives a better utilization of the DSP pipelining/parallel capabilities, and leads to algorithms with significantly lower overhead than traditional methods. Several different programs have been implemented in assembly code for the TMS320C30 and simulated to find their execution times. The new algorithms are shown to be more than 20% faster than traditional sequential algorithms adapted to the processor, because of lower overhead, and better utilization of the parallel instruction sets and the pipelining is obtained. >

A bus-oriented multiprocessor fast Fourier transform

Abstract: A bus-oriented multiprocessor architecture specialized for computation of the discrete Fourier transform (DFT) of a length N=2/sup M/ sequential data stream is developed. The architecture distributes computation and memory requirements evenly among the processors and allows flexibility in the number of processors and in the choice of a fast Fourier transform (FFT) algorithm. With three buses, the bus bandwidth equals the input data rate. A single time-multiplexed bus with a bandwidth of three times the input data rate can alternatively be used. The architecture requires processors that have identical hardware, which makes it more attractive than the cascade (pipeline) FFT for multiprocessor implementation. >