Prime-factor FFT algorithm

About: Prime-factor FFT algorithm is a research topic. Over the lifetime, 2346 publications have been published within this topic receiving 65147 citations. The topic is also known as: Prime Factor Algorithm.

A Performance Study of 16-bit Microcomputer-Implemented FFT Algorithms

Abstract: An FFT algorithm operating on a 16-bit microcomputer can calculate a 256-point transform as much as 10 times faster than a similar algorithm on an eight-bit microcomputer.

A novel 3780-point FFT processor scheme for the time domain synchronous OFDM system *

Abstract: The 3780-point FFT is a main component of the time domain synchronous OFDM (TDS-OFDM) system and the key technology in the Chinese Digital Multimedia/TV Broadcasting-Terrestrial (DMB-T) national standard. Since 3780 is not a power of 2, the classical radix-2 or radix-4 FFT algorithm cannot be applied directly. Hence, the Winograd Fourier transform algorithm (WFTA) and the Good-Thomas prime factor algorithm (PFA) are used to implement the 3780-point FFT processor. However, the structure based on WFTA and PFA has a large computational complexity and requires many DSPs in hardware implementation. In this paper, a novel 3780-point FFT processor scheme is proposed, in which a 60×63 iterative WFTA architecture with different mapping methods is imported to replace the PFA architecture, and an optimized CoOrdinate Rotation DIgital Computer (CORDIC) module is used for the twiddle factor multiplications. Compared to the traditional scheme, our proposed 3780-point FFT processor scheme reduces the number of multiplications by 45% at the cost of 1% increase in the number of additions. All DSPs are replaced by the optimized CORDIC module and ROM. Simulation results show that the proposed 3780-point FFT processing scheme satisfies the requirement of the DMB-T standard, and is an efficient architecture for the TDS-OFDM system.

Real-valued algorithms for the FFT

Abstract: Since 1965, when Cooley and Tukey published their famous paper on the radix-2 fast Fourier transform, much effort has gone into developing even more efficient algorithms. Most algorithms, however, do not directly handle real-valued data very well, and them exist several ways to solve that problem. This paper derives a new algorithm; the decimation-in-time real-valued split-radix FFT, which can transform any length N = 2Msequence but uses less operations than any other known real-valued FFF, which is the fastest Cooley-Tukey real-valued transform in use. Instead of breaking the transform down equally as in traditional algorithms, the even and odd indexed parts are broken down differently in the split-radix algorithm. This gives a significant savings in both additions and multiplications over any fixed radix Cooley-Tukey FFT. The paper compares the split-radix transform with several of the already existing methods such as the Hartley transform, the prime factor, Winograd, Cooley-Tukey etc, and shows in which cases a specific algorithm is faster than the rest.

Implementation of Fast Fourier and Inverse Fast Fourier Transforms in FPGA

Abstract: This article explains implementing of fast Fourier (FFT) and inverse fast Fourier transform (IFFT) algorithms in FPGA. The reason of designing the study on FPGA base is that FPGAs are able to rearrange of logical blocks and moreover, mathematical algorithms can confirm faster by means of parallel data processing. For operating these algorithms, it was used the family of Xilinx Virtex2P xc2vp30fg676-7 FPGA device as a hardware in this study. In programming the hardware and writing codes, VHDL was used. The results show that FFT and IFFT algorithms result in 0.6 mus and 0.72 mus cycle time respectively.

Shared CSD complex constant multiplier for parallel FFT processors

Abstract: This paper presents a shared canonical signed digit (CSD) complex constant multiplier for high-speed low-complexity parallel fast Fourier transform (FFT) processors. To reduce the number of twiddle factor (TF) multiplications, the mixed radix −24/23 FFT algorithm is adopted for FFT processor. The 512-point FFT processor using the proposed shared CSD complex constant multiplier has been designed and implemented using 90-nm CMOS technology. Synthesis results show that the proposed FFT processor achieve a higher throughput rate up to 3.2 GS/s at 400 MHz while requiring much less hardware complexity with respect to other FFT processors. The SQNR performance is 36dB with 12-bit word-length implementation.