Prime-factor FFT algorithm

About: Prime-factor FFT algorithm is a research topic. Over the lifetime, 2346 publications have been published within this topic receiving 65147 citations. The topic is also known as: Prime Factor Algorithm.

Reduced-Reference image quality assessment based on 2-D discrete FFT and Edge Similarity

Abstract: Reduced-Reference (RR) image quality measures aim to predict the perceptual quality of distorted image using only partial information about the original image. In this paper, an effective Reduced-Reference image quality assessment algorithm based on FFT transform and Edge Similarity is introduced. The main design principle of the proposed method is choice of the best blocks of Image. After dividing the source images into blocks of 16×16 pixels, calculating the FFT Transform for each block, the FFT Transform gives best blocks of image. Next, the important features blocks of the image were recognized by Edge and the same actions were done on the image of distortions and finally, the similarity of both images was calculated. The experimental results on LIVE and CSIQ databases show that our RR proposed metric correlates well with the subjective quality scores, also in comparison with commonly used full-reference metric and with a state-of-the-art reduced reference.

A new rapid acquisition algorithm based on FFT for GPS signals

Abstract: To improve speed and accuracy of the GPS signal acquisition,a new parallel acquisition algorithm based on FFT is proposed.The new algorithm only takes one time of FFT and multiple times of IFFT to complete the two-dimensional search,and operation time reduces the half as compared with that of the traditional algorithm based on FFT.A new algorithm based on polynomial interpolation is proposed to improve the precision of the acquisition accuracy after the coarse acquisition.Simulation results prove it well.

Implementation of FPGA-based FFT convolution

Abstract: In this research, an efficient pipelined overlap-add filter is designed for the linear convolution of the streaming data. The designed filter uses the fft convolution method and modified radix-4 architecture for the zero-padded input data. Several techniques are used in order to decrease the hardware resources for the proposed design. Firstly, FFT (Fast Fourier Transform) resources are shared between the two FFT units used for the FFT convolution method. Second, bit-reversed inputs are used for inverse FFT operation. The target device for the implementation is a Xilinx Virtex-5 FPGA. The architecture yields similar accuracy and throughput with the cost of less hardware resources than the designs using the commercial FFT IP cores. (4 pages)

A study on implementing wavelet transform and FFT with FPGA

Abstract: This paper shows how to implement the wavelet transform and the Fast Fourier Transform (FFT) with a Field Programmed Gate Array (FPGA). First, it introduces the implementation of the wavelet transform with lattice filters and achieves the FFT with the Coordinate Rotational Digital Computation (CORDIC). Then, the emulation data of the Daubechies D4 & D6 wavelet transforms and the FFT with 16 points are given, and their performances are analyzed. The results prove this to be a novel and effective method to implement the wavelet transform and the FFT with FPGA.

Custom instruction for NIOS II processor FFT implementation for image processing

Abstract: Image processing can be considered as signal processing in two dimensions (2D). Filtering is one of the basic image processing operation. Filtering in frequency domain is computationally faster when compared to the corresponding spatial domain operation as the complex convolution process is modified as multiplication in frequency domain. The popular 2D transforms used in image processing are Fast Fourier Transform (FFT), Discrete Cosine Transform (DCT) and Discrete Wavelet Transform (DWT). The common values for resolution of an image are 640x480, 800x600, 1024x768 and 1280x1024. As it can be seen, the image formats are generally not a power of 2. So power of 2 FFT lengths are not required and these cannot be built using shorter Discrete Fourier Transform (DFT) blocks. Split radix based FFT algorithms like Good-Thomas FFT algorithm simplifies the implementation logic required for such applications and hence can be implemented in low area and power consumption and also meet the timing constraints thereby operating at high frequency. The Good-Thomas FFT algorithm which is a Prime Factor FFT algorithm (PFA) provides the means of computing DFT with least number of multiplication and addition operations. We will be providing an Altera FPGA based NIOS II custom instruction implementation of Good-Thomas FFT algorithm to improve the system performance and also provide the comparison when the same algorithm is completely implemented in software.