Prime-factor FFT algorithm

About: Prime-factor FFT algorithm is a research topic. Over the lifetime, 2346 publications have been published within this topic receiving 65147 citations. The topic is also known as: Prime Factor Algorithm.

Effectiveness of partitioning strategies of Fast Fourier Transform in GPU implementations

Abstract: In this paper authors present the results of the effectiveness comparison between the variants of the Radix-2 Deci-mation in Time (DIT) Fast Fourier Transform (FFT) algorithm's implementations on graphics processing units (GPUs) which differ in the way the calculations are distributed among GPUs computational resources. The conducted experiments show that the partitioning of the FFT computational scheme into 4-point and 8-point subtransform blocks in which calculations are performed in a sequential, single instruction multiple thread (SIMT) manner results in significantly faster execution of the FFT calculations on the selected GPU architectures than the standard parallel 2-point butterfly base operation approach. Moreover the proposed partitioning scheme can be extended to arbitrary subtransform block size for a given N-point Radix-2 FFT implementation dedicated to particular GPU architectures.

Comments on "A prime factor FFT algorithm using high-speed convolution"

Abstract: The purpose of this correspondence is to point out that in Table II of the above paper, the number of additions reported for the radix-2 FFT algorithm are highly erroneous.

Application of an iterative method to nonlinear superposition of water wave profiles: FFT and mathematical analysis

Abstract: In a previously published paper, Jang and Kwon (Ocean Engineering, 1995, 32:1862–1872) proposed a new iterative method to estimate nonlinear wave profiles and demonstrated its solution procedure. The solution was based on the Banach contraction mapping theorem, and the nonlinear operator was constructed from the Bernoulli equation. This paper is a sequel to that paper and seeks to establish the existence and uniqueness of the proposed method. Furthermore, frequency content of the profiles of the generated waves by the proposed scheme was analyzed by the fast Fourier transform (FFT). The obtained waves contained high-order nonlinear Fourier components of a Stokes' wave.

Area and time optimized realization of 16 point FFT and IFFT blocks by using IEEE 754 single precision complex floating point adder and multiplier

Abstract: Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) act as primary blocks in most of the digital signal processing applications. These two operations have undergone numerous advancements in terms of software implementation. However, there is a dearth of hardware implementation of the same, due to the involvement of floating point complex numbers. Existing Fast Fourier Transform /Inverse Fast Fourier Transform implementations mostly deal with integer data only and are incompatible with floating point data. The need of the hour is a design that can operate on floating point numbers and also achieves maximum efficiency, minimum hardware utilization and high data precision. This paper proposes implementation of a novel complex floating point arithmetic operations namely addition and multiplication. The proposed floating point adders and multipliers are used in developing 16 point Fast Fourier Transform and Inverse Fast Fourier Transform blocks. The proposed design eliminates hardware redundancy by intelligently manipulating the inputs and there by reduces the area required for implementation. The existing design and proposed design of the complex floating point multiplier is compared on the Cadence platform. Analysis of the obtained results show that the proposed design of the complex floating point multiplier as compared to the existing design, is optimal in terms of number of cells, number of gates, path delay, cell area and produces highly precise results.