Topic
Prime-factor FFT algorithm
About: Prime-factor FFT algorithm is a research topic. Over the lifetime, 2346 publications have been published within this topic receiving 65147 citations. The topic is also known as: Prime Factor Algorithm.
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30 Nov 1990
TL;DR: In this article, a dense modular system for the high speed computation of a composite fast Fourier transform (FFT) is described, where the composite FFT is formed by aggregating a series of individual FFT passes.
Abstract: A dense modular system for the high speed computation of a composite fast Fourier transform (FFT) is disclosed. The composite FFT is formed by aggregating a series of individual FFT passes. The FFT passes are calculated within module boundaries in a substantially parallel manner and the input and output between the modules is transmitted in a substantially serial manner. The serial transmission takes place at a higher speed than the parallel FFT computation in order to preserve the constant data flow in the composite FFT.
4 citations
09 Jun 2013
TL;DR: Theoretical analysis demonstrates the equivalence of the proposed polyphase-filter-based FFT (PF-FFT) and the original DFT, which keeps low complexity and good fixed-point performance.
Abstract: In LTE uplink, a DFT with 34 possible lengths is performed. The traditional method directly transforms the sequences with different lengths by using the mixed-radix FFT which is not appropriate to apply on the DSP processor only supplying radix-2 butterfly hardware especially. In this paper, we resample the arbitrary-length input sequence so that a 2n-point FFT can be applied by using the polyphase filter. Theoretical analysis demonstrates the equivalence of the proposed polyphase-filter-based FFT (PF-FFT) and the original DFT. Moreover, the PF-FFT also keeps low complexity and good fixed-point performance.
4 citations
14 Aug 2010
TL;DR: The improved FFT parallel algorithm based on the Six-Step FFT algorithm is improved, and a framework based on Grid is built up to make the parallel F FT algorithm high efficiency.
Abstract: With the extensive applications of FFT in digital signal processing and image signal processing which needs a extensive application of large-scale computing, it Become more and more important to improve parallelism??? Efficient and Scalable parallel of FFT algorithm. This paper Improve the parallelism of the FFT algorithm based on the Six-Step FFT algorithm, And build up a framework Based on Grid, Through the calculation of the matrix assigned to the various nodes of grid computing and the use of hiding the transpose matrix mapping optimization strategy etc, it makes the parallel FFT algorithm high efficiency. In the end, the paper evaluates the performance of the improved FFT parallel algorithm.
4 citations
02 Apr 2015
TL;DR: A parallel FFT architecture is proposed to give an efficient throughput and less energy consumption with the help of Cooley Tukey algorithm for radix 8 as it reduces arithmetic computations as well as fast processing.
Abstract: In this paper, a parallel FFT architecture is proposed to give an efficient throughput and less energy consumption with the help of Cooley Tukey algorithm for radix 8. In this algorithm the DFT of N size is divided into smaller sizes of N/2 and repeated until final DFT scalars are found. It divides the DFT in even index and odd index term. The computation time which is calculated by the pre defined formula (Nlog 2 (N)) is reduced by the use of parallel architecture. Energy is defined as power used per unit time. Parallel architecture helps to perform number of operations simultaneously. As less time is required, the energy is efficiency is increased. The aim of this paper is to check throughput and efficiency using Cooley Tukey algorithm for higher radix. The recent trends of this algorithm is development of FPGA that is Field Programmable Gate Array as it can perform signal processing tasks in parallel, execute pipeline structure as well as speed up the computation of tedious algorithms. The main advantage of Cooley Tukey algorithm is that it reduces arithmetic computations as well as fast processing. As this algorithm divides the DFT into smaller DFTs, it can be combined with any other algorithm simultaneously.
4 citations
22 Jan 1992
TL;DR: The authors propose a parallel FFT (fast Fourier transform) architecture based on an N-point FFT decomposition that is faster than that of a single FFT chip and a fault tolerance interconnection for the FFT butterfly network by considering the complexity of the number of primitive cells.
Abstract: The authors propose a parallel FFT (fast Fourier transform) architecture based on an N-point FFT decomposition. Performance evaluation is performed with respect to the total area of the architecture. It is clear that the architecture is simple and the execution time is faster than that of a single FFT chip. The authors also propose a fault tolerance interconnection for the FFT butterfly network by considering the complexity of the number of primitive cells. >
4 citations