Prime-factor FFT algorithm

About: Prime-factor FFT algorithm is a research topic. Over the lifetime, 2346 publications have been published within this topic receiving 65147 citations. The topic is also known as: Prime Factor Algorithm.

Algorithms of the q2^r× q2^r-point 2D discrete Fourier transform

Abstract: In this paper, the concept of partitions revealing the two-dimensional discrete Fourier transform (2-D DFT) of order q2 r × q2 r , where r > 1 and q is a positive odd number, is described. Two methods of calculation of the 2-D DFT are analyzed. The q2 r × q2 r -point 2-D DFT can be calculated by the traditional column-row method with 2(q2r) 1-D DFTs, and we propose the fast algorithm which splits each 1-D DFT by the short transforms by means of the fast paired transforms. Another effective algorithm of calculation of the q2 r × q2 r -point 2-D DFT is based on the tensor or paired representations of the image when the image is represented as a set of 1-D signals which define the 2-D transform in the different subsets of frequency-points and they all together cover the complete set of frequencies. In this case, the splittings of the q2 r × q2 r -point 2-D DFT are performed by the 2-D discrete tensor or paired transforms, respectively, which lead to the calculation with a minimum number of 1-D DFTs. Examples of the transforms and computational complexity of the proposed algorithms are given.

Design and realization of small point FFT processor based on twiddle factor classification

Abstract: In this paper, a new design method for small point fast Fourier transform (FFT) processor is proposed in order to satisfy the increased demands for low resource and power consumption in addition to high real-time performance in communication and control systems. Using 64 point FFT with radix-2, decimation in time (DIT) algorithm as the design objective, only an adder block and a multiplier block with pipeline structure and floating point arithmetic are adopted applying this design method. According to different classifications of twiddle factor, corresponding butterfly operations can be implemented to save the total calculation time to only 1100 clock cycles for 64 point FFT. In addition, multiple FFT processor blocks can be integrated for parallel computing to achieve higher data throughput rate. Compared with some other designs of 64 point FFT, the final results show that the proposed design has better real-time performance and lower system level complexity with the same amount of resources.

FFT/DWT/DCT OFDM channel estimation using EM algorithm in the presence of chaotic interleaving

Abstract: This paper presents a new interleaving scheme for efficient data transmission with Orthogonal Frequency Division Multiplexing (OFDM) over fading channels This approach is based on the chaotic Baker map The binary data is interleaved with the proposed approach prior to the modulation step In addition to improve the system performance in fading channel, the proposed chaotic interleaving approach adds a degree of encryption to the transmitted data The performance of the proposed approach is tested on the conventional Fast Fourier Transform OFDM (FFT-OFDM), Discrete Wavelet Transform OFDM (DWT-OFDM), and Discrete Cosine Transform OFDM (DCT-OFDM) with and without chaotic interleaving Expectation-Maximization (EM) algorithm is also proposed to efficiently estimate the channel impulse response (CIR) of such a system operating on a channel with multipath fading Starting from the Maximum Likelihood (ML) principle, we derive an iterative estimation algorithm based on the (EM) algorithm This algorithm is capable of improving the channel estimate In the initialization phase of this iterative algorithm, the initial channel estimate is based on the observation of the pilot carriers only Then the EM algorithm updates the channel estimates until convergence is reached, the resulting bit error rate essentially coincides with the case of the perfectly known channel By simulations, the efficiency of these algorithms can be investigated with simulation and the results of estimation will come to a comparison

Design of Harmonic Detection Using Windowed Interpolation FFT Algorithm

Abstract: The detection system for harmonic is designed in this paper. The adopted microchip is LPC1114 with the built-in A/D device. The high precision signals of current and voltage are sampled by using the A/D device. The sampling data is analyzed by the windowed interpolation FFT algorithm. And the frequency and amplitude of fundamental and harmonic wave for the current and voltage is got. The test results prove the virtues of this system with the simple hardware and the high precision.

Design and implementation of FFT pruning algorithm on FPGA

Abstract: Digital Signal Processing (DSP) has evolved as an integrated component in electronics advancement. Among all the DSP operations, Fast Fourier Transform (FFT) plays a prominent role in signal processing. FFT computational time reduces when the number of zero valued inputs (Z) outnumbers the non-zero valued inputs (NZ) due to unnecessary computations for Z. The above issue can be resolved by minimizing computations on Ζ by the method Pruning (Partial, Complete) in FFT. The pruning method is implemented in the hardware and computational time improvement is observed. The FFT Pruning is developed in Verilog and validated on Spartan 3E FPGA (xc3s500e-fg320-5).