Prime-factor FFT algorithm

About: Prime-factor FFT algorithm is a research topic. Over the lifetime, 2346 publications have been published within this topic receiving 65147 citations. The topic is also known as: Prime Factor Algorithm.

An Algorithm for Calculating the Linear Discrete Convolution With FFT

Abstract: This papers introduces an algorithm for calculating the linear discrete convolution with FFT.The mathematic model and the implementation of the are also presented.

Flexible-length fast fourier transform for mapping onto single-instruction multiple-data computing architecture

Abstract: A novel and flexible approach to the design and implementation of fast Fourier transforms (FFTs) of standard (fixed-radix) or non-standard length is described. By adopting a two-factor formulation, based upon either the prime factor algorithm or the common factor algorithm, where one factor, N1, is an integer power, and the other, N2, a small integer (odd- or even-valued), the (N1×N2)-point 1D discrete Fourier transform (DFT) can be carried out via the ‘row–column’ method with the design of just two generic DFT/FFT modules. Processing the small row-DFTs coefficient-by-coefficient, rather than DFT-by-DFT, it is seen how the usual requirement for matrix transposition of the row-DFT output can be eliminated. This reduces the processing requirement to a number of independent processes in which each process generates a set of small-DFT coefficients prior to computing a fixed-radix FFT of the resulting coefficient set. Hardware efficiency/simplicity is achieved by computing the small-DFT coefficients via a modified form of the Goertzel DFT (GDFT) filter, referred to here as the ‘dual-coefficient’ GDFT filter, which simultaneously computes two DFT coefficients. The resulting decomposition maps onto just ⌊½N2⌋+1 processing elements (PEs), via the single-instruction multiple-data computing architecture, in which each PE comprises two types of module: one corresponding to a dual-coefficient GDFT filter bank, the other to the associated dual-data FFTs. This yields flexible-length FFTs that lend themselves naturally to multi-level parallelisation, overcoming the communication problems associated with mapping sequentially optimal FFT algorithms onto multi-processor computing architectures.

Long-Point FFT Processing Based on Twiddle Factor Table Reduction

Abstract: In this paper, we present a new fast Fourier transform (FFT) algorithm to reduce the table size of twiddle factors required in pipelined FFT processing. The table size is large enough to occupy significant area and power consumption in long-point FFT processing. The proposed algorithm can reduce the table size to half, compared to the radix-22 algorithm, while retaining the simple structure. To verify the proposed algorithm, a 2048-point pipelined FFT processor is designed using a 0.18 μm CMOS process. By combining the proposed algorithm and the radix-22 algorithm, the table size is reduced to 34% and 51% compared to the radix-2 and radix-22 algorithms, respectively. The FFT processor occupies 1.28 mm2 and achieves a signal-to-quantization-noise ratio (SQNR) of more than 50 dB.

FAST: a compact general crystallographic fast Fourier transform (FFT)

Abstract: A space-group-general radix-2 crystallographic fast Fourier transform (FFT) has been written in only 130 lines of executable Fortran code. Computational times compare favorably with other FFT programs that require 1000 or more lines of code excluding peak-interpolation routines. The complete program and description of control parameters are given. The program is dimensioned to a maximum grid size of 1283 points and a Miller-index range of ±60. These arrays may be altered by simply changing the values of NPAR and MH in the PARAMETER statements of the program.

Design and implementation in VHDL code of the two-dimensional fast Fourier transform for frequency filtering, convolution and correlation operations

Abstract: The two-dimensional Fast Fourier Transform (FFT 2D) is an essential tool in the two-dimensional discrete signals analysis and processing, which allows developing a large number of applications. This article shows the description and synthesis in VHDL code of the FFT 2D with fixed point binary representation using the programming tool Simulink HDL Coder of Matlab; showing a quick and easy way to handle overflow, underflow and the creation registers, adders and multipliers of complex data in VHDL and as well as the generation of test bench for verification of the codes generated in the ModelSim tool. The main objective of development of the hardware architecture of the FFT 2D focuses on the subsequent completion of the following operations applied to images: frequency filtering, convolution and correlation. The description and synthesis of the hardware architecture uses the XC3S1200E family Spartan 3E FPGA from Xilinx Manufacturer.