Prime-factor FFT algorithm

About: Prime-factor FFT algorithm is a research topic. Over the lifetime, 2346 publications have been published within this topic receiving 65147 citations. The topic is also known as: Prime Factor Algorithm.

New algorithm for design of low complexity twiddle factor multipliers in radix-2 FFT

Abstract: In this paper, a new design algorithm is proposed to synthesize low complexity twiddle factor multipliers in radix-2 FFT. A prudently defined cost function has been proposed as a measure of hardware complexity when generating trigonometric expressions for the complex multiplier coefficients. The selected trigonometric expressions of the coefficients lead to cost efficient implementation of twiddle factor multipliers by maximizing the sharing of both trigonometric expressions and weight-two common subexpressions in the coefficients. The effectiveness of the proposed design algorithm are demonstrated using two design examples where the proposed solution saves up to 31% of arithmetic operator and multiplexer costs over other existing methods.

Real-time signal frequency analysis in variable speed drives using the sparse fast Fourier transform (sFFT)

Abstract: This paper investigates the implementation and the use of the sparse fast Fourier transform algorithm in the converter control of a variable speed drive. The algorithm is proposed due to the reduction in computational complexity compared to the conventional fast Fourier transform for the special case of sparse signals. After discussing the theory and a simulation model, experimental results obtained using a field programmable gate array (FPGA) implementation are presented, showing the effectiveness of the proposed solution.

Accelerating FFT Using NEC SX-Aurora Vector Engine

Abstract: Novel architectures leveraging long and variable vector lengths like the NEC SX-Aurora or the vector extension of RISCV are appearing as promising solutions on the supercomputing market. These architectures often require re-coding of scientific kernels. For example, traditional implementations of algorithms for computing the fast Fourier transform (FFT) cannot take full advantage of vector architectures. In this paper, we present the implementation of FFT algorithms able to leverage these novel architectures. We evaluate these codes on NEC SX-Aurora, comparing them with the optimized NEC libraries. We present the benefits and limitations of two approaches of RADIX-2 FFT vector implementations. We show that our approach makes better use of the vector unit, reaching higher performance than the optimized NEC library for FFT sizes under 64k elements. More generally, we prove the importance of maximizing the vector length usage of the algorithm and that adapting the algorithm to replace memory instructions with register shuffling operations can boost the performance of FFT-like computational kernels.

Design of a reconfigurable FFT processor using Multi-objective Genetic Algorithm

Abstract: This paper describes the implementation of Multi-objective Genetic Algorithm (MOGA) in a 16-point Radix-4 Single Path Delay Feedback (R4SDF) pipelined Fast Fourier Transform (FFT) processor in Verilog. The role of MOGA is to optimize the wordlength of the FFT coefficient and at the same time make sure the processor operates at acceptable Signal to Noise Ratio (SNR). Reducing the wordlength of FFT coefficient will contribute to lower Switching Activity (SA), thus lower power consumption is required for the operation of FFT processor.