Topic
Prime-factor FFT algorithm
About: Prime-factor FFT algorithm is a research topic. Over the lifetime, 2346 publications have been published within this topic receiving 65147 citations. The topic is also known as: Prime Factor Algorithm.
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Journal Article•
TL;DR: The computation procedure of fast algorithm is optimized, and the complete statistical result of the implementation is given, showing the amount of real number multiplication computation can be minimized by the proposed fast algorithm for the given accuracy.
Abstract: In order to meet the requirement of DFRFT(discrete fractional Fourier transform) real-time computation on DSP(digital signal processor),several DFRFT computation methods are compared and the Ozaktas′s DFRFT fast algorithm is chosen to do the implementation processing based on DSP.On the basis of theoretical analysis for the fast algorithm,the computation procedure of fast algorithm is optimized,and the complete statistical result of the implementation is given.The amount of real number multiplication computation can be minimized by the proposed fast algorithm for the given accuracy.Engineering practice proves that this solution meets the accuracy requirement and real-time property of DSP computation.
1 citations
TL;DR: This correspondence describes a modified version of the Burrus and Rothweiler prime factor FFT algorithm for the powers of prime length that allows a much wider selection of transform sizes, and calculates the DFT in order.
Abstract: This correspondence describes a modified version of the Burrus and Rothweiler prime factor FFT algorithm for the powers of prime length. It allows a much wider selection of transform sizes, and calculates the DFT in order. Speed measurements show that the resulting program can be faster than Singleton's algorithm for some specific transform length.
1 citations
05 May 1984
TL;DR: Several methods for computing the FFT in hardware are reviewed and an algorithm due to Radar is used which is easier to implement in a pipeline than the minimum multiply algorithms of Winograd, which requires less hardware than pipelines based on the algorithms above.
Abstract: : In some signal processing applications, it is desirable to build very high fast Fourier transform (FFT) processors. To meet the performance requirements, these processors are typically high-pipelined. Until the advent of VLSI, it was not possible to build a single chip which could be used to construct pipeline FFT processors of a reasonable size. However, VLSI implementations have constraints which differ from those of discrete implementations, requiring another look at some of the typical FFT algorithms in the light of these constraints. In this paper, several methods for computing the FFT in hardware are reviewed. Pipeline structures for the Cooley-Tukey algorithm and the Good prime factor algorithm are presented. The various small base modules required for the construction of these processors are examined with VLSI implementations in mind. For prime bases, an algorithm due to Radar is used which is easier to implement in a pipeline than the minimum multiply algorithms of Winograd. The Winograd technique of centralizing the multiples of several relatively prime bases is used to develop a pipeline which requires less hardware than pipelines based on the algorithms above. Keywords include: CORDIC; fast Fourier transform; integrated circuits; parallel processors; pipeline processors; and signal processing.
1 citations
TL;DR: This algorithm represents a proof of concept that a simple and easy-to-code, out-of-core algorithm can be easily implemented and used to solve large-scale problems on low-cost hardware.
1 citations
Journal Article•
TL;DR: The study showed that the algorithms would reduce programming complexity, data relativity and limitation of processor unit's on-chip memory capacity, which was suitable to realize on multiprocessor platform where DSP was acted as processor unit.
Abstract: To speed the calculation of orthogonal algorithm,a parallel orthogonal transform algorithm on expanded-dimension parallelism based on that one dimension orthogonal transform of length N=N_0N_1 would be decomposed into two dimension orthogonal transform of length N_0×N_1 with some little additional operations was put forward in this paper.According to the definition of expanded-dimension parallelism for parallel orthogonal transform algorithm,the realization and feature of DFT algorithm,Hadamard transform algorithm and Hartley transform algorithm were discussed.The achievement of the parallel orthogonal transform was carried out based on TMS320C80 multiprocessor platform.The study showed that the algorithms would reduce programming complexity,data relativity and limitation of processor unit's on-chip memory capacity,which was suitable to realize on multiprocessor platform where DSP was acted as processor unit.
1 citations