Topic
Prime-factor FFT algorithm
About: Prime-factor FFT algorithm is a research topic. Over the lifetime, 2346 publications have been published within this topic receiving 65147 citations. The topic is also known as: Prime Factor Algorithm.
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13 Feb 2013
TL;DR: In this article, an eight-point winograd fourier transform algorithm (WFTA) processor without rearrangement was proposed. But the rearrangements operation which the 8-point WFTA relates to in an N-point indexing same sequence prime factor algorithm is omitted, the control logic is simplified, the arithmetic speed is improved, the storage loss is reduced, and the hardware cost is lowered.
Abstract: The invention relates to an eight-point winograd fourier transform algorithm (WFTA) processor without rearrangement. The processor is characterized in that the processor is composed of an input matrix I, a variable diagonal matrix A, an output matrix O and plural multiplying unit M1-M3. The input matrix I is multiplied with an input vector v through the plural multiplying unit M1 to obtain a vector p, the variable diagonal matrix A is multiplied with the vector p through the plural multiplying unit M2 to obtain a vector q, and the output matrix O is multiplied with the vector q through the plural multiplying unit M3 to obtain an output vector V. According to the eight-point WFTA processor without the rearrangement, the rearrangement operation which the eight-point WFTA relates to in an N-point indexing same sequence prime factor algorithm is omitted, the control logic is simplified, the arithmetic speed is improved, the storage loss is reduced, and the hardware cost is lowered.
01 Jan 2011
TL;DR: It is shown that the method of the fast paired-transform utilizes less hardware for higher sampling rates and is best suited for FFT designs in FPGA where speed, area, and cost are the major factors.
Abstract: ð In this paper an effective design and implementation of the fast Fourier transform (FFT) by the paired transforms is presented and compared with the existent radix-2 algorithm. A block level design of the fast transform methods is implemented and tested in this research work. Discussed is a possibility of reducing the arithmetic computations, hardware utilization and the number of clock cycles in the FFT process that ultimately results in an optimized FFT design and thereby increases the overall speed-up. It is shown that the method of the fast paired-transform utilizes less hardware for higher sampling rates and is best suited for FFT designs in FPGA where speed, area, and cost are the major factors. An in-depth count of arithmetic operators involved in the 4-point up to the 64point FFT is tabulated in this paper, which gives a clear comparison in choosing the best fasttransform methods. The signal-flow graph for the 16-point FFT is considered for detailed explanation and analysis of the FFT methods. As the development of fast digital signal processing (DSP) algorithms and their implementation in FPGA is a field of great interest, all the designs discussed in this paper are targeted for high performance FFT implementations in FPGA.
01 Jan 1988
TL;DR: The proposed parallel algorithm is attractive for real time image processing and can apply the 2-D fast inverse discrete Fourier transform (IFFT) algorithm to reduce the computational load.
Abstract: Multirate and DFT based fast parallel algorithm for the 2-D inverse discrete Gabor transform (IDGT) is presented. A 2-D synthesis filterbank is designed for the 2-D IDGT. The parallel channels in the filterbank have a unified structure and can apply the 2-D fast inverse discrete Fourier transform (IFFT) algorithm to reduce the computational load. The computational complexity of each parallel channel is very low and is independent of the oversampling rate. Thus, the proposed parallel algorithm is attractive for real time image processing.
01 Jan 2014
TL;DR: The new Proposed design has been designed and developed by novel parallel-pipelined Fast Fourier Transform (FFT) architecture and the radix-6 Z has been developed to reduce the complexity of hardware and the computational intension.
Abstract: The new Proposed design has been designed and developed by novel parallel-pipelined Fast Fourier Transform (FFT) architecture. The most important and fastest efficient algorithm is a FFT. FFT is used to computes the Discrete Fourier Transform (DFT). FFT is mainly applied in autocorrelation, spectrum analysis, linear filtering and pattern recognition system. The proposed architectures were designed by using register minimization and folding transformation technique. The critical path is reduced by pipelining and the multiple inputs and multiple outputs are computed by parallel processing. Furthermore, radix-2, radix- 3, radix-6 Z decimation in time and decimation in frequency algorithm can be used. As a result, the radix-6 Z has been developed to reduce the complexity of hardware and the computational intension. The power dissipation can be decreased and unwanted operations are stopped by using the clock gates.