Topic
Prime-factor FFT algorithm
About: Prime-factor FFT algorithm is a research topic. Over the lifetime, 2346 publications have been published within this topic receiving 65147 citations. The topic is also known as: Prime Factor Algorithm.
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01 Jan 2014
TL;DR: In this article, a 32 bit word length 64 point FFT/IFFT processor developed primarily for the use in OFDM bases IEEE 802.11a wireless LAN based application is discussed.
Abstract: This paper discuss an efficient approach for implementing 64- Point FFT/IFFT in the OFDM Transreciever .In our proposed design we will be incorporating a novel 32 bit word length 64 point FFT/IFFT processor developed primarily for the use in OFDM bases IEEE 802.11a wireless LAN based application. The 64 point FFT is realized by decomposing a 64 point FFT in two dimensional structure of 8 point FFT. This approach greatly reduces the number of complex multiplication required as compared to conventional radix-2 64 point FFT algorithm. Same unit can be used for both FFT and IFFT by just swapping its real and imaginary parts The main reason for our emphasis on FFT/IFFT processor in the design of IEEE 802.11a Transreciever is because of its ability to provide orthogonality to data carrier that forms the essence of any OFDM scheme.
09 Jul 1984
TL;DR: The results of performance analysis show that the combination of adaptive architecture capability and VLSI technology can provide a practical solution for meeting the goal of advanced real-time FFT processing.
Abstract: A versatile special-purpose VLSI fast Fourier transform (FFT) processor is presented. It can process variant data sizes of FFT and cooperate with other identical FFT processors to accomplish cascade and parallel FFT processing schemes. The operations of the single processor FFT processing scheme, the multiprocessor cascade FFT processing scheme, and the multiprocessor parallel FFT processing scheme are described. The results of performance analysis show that the combination of adaptive architecture capability and VLSI technology can provide a practical solution for meeting the goal of advanced real-time FFT processing.
16 Feb 2022
TL;DR: In this article , the authors proposed an efficient algorithm to reduce the redundant computations in FFT which improves the speed and reduces the power consumption by using verilog HDL and pruning.
Abstract: Fast Fourier Transform (FFT) is a Digital Signal Processing (DSP) technique to compute Discrete Fourier Transform (DFT) in a faster way by utilizing the properties of the twiddle factor. Conventional FFT has a problem of computational inefficiency when the number of zero valued inputs out-numbers the number of non-zero valued inputs. This is because of the redundant computations on the zero valued inputs. This issue can be resolved by using a technique called pruning in FFT. In this paper we propose an efficient algorithm to reduce the redundant computations in FFT which improves the speed and reduces the power consumption. The proposed algorithm is implemented using verilog HDL.
01 May 2017
TL;DR: Efficient designs of the Fast Fourier Transform (FFT) Decimation-in-Time (DIT), radix-2, Butterfly Unit, Gauss complex multiplication algorithm are proposed and several techniques are incorporated in order to achieve higher performance.
Abstract: In this paper, efficient designs of the Fast Fourier Transform (FFT) Decimation-in-Time (DIT), radix-2, Butterfly Unit are proposed Several techniques are incorporated in order to achieve higher performance The operations are fused by keeping the intermediate variables in Carry-Save format Besides of the conventional, the Gauss complex multiplication algorithm is also explored Considered that the twiddle factors cosϕ, sinϕ used in FFT algorithm are constant numbers, we apply to them a special NR4SD encoding scheme with the following sets of digit values: {−2, −1, 0, +1} Finally, to increase the operation speed, one level of pipelining is introduced in all designs We implement four designs: one conventional and three new Butterfly Units In all cases, the proposed three schemes are superior in terms of operation speed, area and power, compared to the conventional
TL;DR: A hardware structure for fast Fourier transform computation thai that provides significant hardware savings on the requirements of data memory and multipliers and efficient data format conversions between different number systems is described.
Abstract: This paper describes a hardware structure for fast Fourier transform (FFT) computation thai is particularly suited to input data presented sequentially. The algorithm allows different representations of complex numbers to be used in the same processing system so that the FFT can be computed by using multiplication-free butterfly elements based on the radix numbers of 2, 3, 4 and 6. In comparison with previous designs in the literature, the new algorithm provides significant hardware savings on the requirements of data memory and multipliers. Furthermore, the FFT size N, which is usually a composite number of 2 or 4, can be more flexible. Efficient data format conversions between different number systems are also provided.