Prime-factor FFT algorithm

About: Prime-factor FFT algorithm is a research topic. Over the lifetime, 2346 publications have been published within this topic receiving 65147 citations. The topic is also known as: Prime Factor Algorithm.

Matrix-Vector Based Fast Fourier Transformations on SDR Architectures

Abstract: . Today Discrete Fourier Transforms (DFTs) are applied in various radio standards based on OFDM (Orthogonal Frequency Division Multiplex). It is important to gain a fast computational speed for the DFT, which is usually achieved by using specialized Fast Fourier Transform (FFT) engines. However, in face of the Software Defined Radio (SDR) development, more general (parallel) processor architectures are often desirable, which are not tailored to FFT computations. Therefore, alternative approaches are required to reduce the complexity of the DFT. Starting from a matrix-vector based description of the FFT idea, we will present different factorizations of the DFT matrix, which allow a reduction of the complexity that lies between the original DFT and the minimum FFT complexity. The computational complexities of these factorizations and their suitability for implementation on different processor architectures are investigated.

Low complexity joint detection for UTRA-TDD receivers

Abstract: In this paper, we present the successful application of prime factor algorithm FFT (Fast Fourier Transform) and pruning techniques to achieve low complexity UTRA-TDD joint detection. This approach has been applied to the Minimum Mean Square Error-Block Linear Equalizer (MMSE-BLE) receiver after proper reformulation in the frequency domain. A complexity reduction of 50% with respect to previous solutions has been demonstrated without any performance loss.

Hybrid fast algorithm for S transforms

Abstract: The S transform is useful in time-frequency analysis. In this paper, we propose a hybrid algorithm to implement it adaptively. Since the window size of the S transform varies with |f|, it is reasonable to use different algorithm for different frequency to implement it. In this paper, we use the sub IDFT algorithm in the low frequency region and the sectioned convolution algorithm in the high frequency region to implement the S transform. From simulation, our algorithm reduces 54% of the computation time and much improves the efficiency of the S transform.

A high-throughput, contention-free low-power, Radix-2 1k,2k, 4k and 8k-point fast fourier transform engine using 28nm standard-cell process

Abstract: This paper presents a high-throughput, contention-free, low-power, Radix-2 decimation in frequency fast Fourier transform core implemented in 28nm industry representative standard-cell process. It utilizes an algorithm to eliminate memory access contention and maximize throughput by eliminating bubbles in the butterfly's pipeline. The implementation of the FFT core is presented, including timing and place-and-route result in 28nm standard CMOS process. The FFT core can perform 1024, 2048, 4096 and 8192 points FFT. The FFT core uses two-port SRAM elements and achieves a throughput of 2-butterfly operations every clock cycle. The FFT core performs 8K-points FFT in around 40uS.

A uniform model for parallel fast Fourier transform (FFT) and fast discrete cosine transform (FDCT)

Abstract: Extended summary form only given. The techniques for parallel processing of FFT are applied to design a parallel processing model for FDCT. Each transform is translated to a sequence of elementary operations, an equation with regularity. From the similarity of both equations, a uniform representation for FFT and FDCT is derived and a common parallel architecture (shown in diagram form) is proposed to realize both FFT and FDCT while also achieving the best known computational complexity. >