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Prime-factor FFT algorithm

About: Prime-factor FFT algorithm is a research topic. Over the lifetime, 2346 publications have been published within this topic receiving 65147 citations. The topic is also known as: Prime Factor Algorithm.


Papers
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Journal ArticleDOI
TL;DR: A flexible efficient and accurate inverse Laplace transform algorithm is developed that computes the coefficients of the continued fractions needed for the inversion process by combining diagonalwise operations and recursion relations in the quotient-difference schemes.
Abstract: A flexible efficient and accurate inverse Laplace transform algorithm is developed. Based on the quotient-difference methods the algorithm computes the coefficients of the continued fractions needed for the inversion process. By combining diagonalwise operations and the recursion relations in the quotient-difference schemes, the algorithm controls the dimension of the inverse Laplace transform approximation automatically. Application of the algorithm to the solute transport equations in porous media is explained in a general setting. Also, a numerical simulation is performed to show the accuracy and efficiency of the developed algorithm.

33 citations

Journal ArticleDOI
TL;DR: The fixed-point error analysis and parameter selections of MSR-CORDIC with applications to the fast Fourier transform (FFT) are presented and two different parameter selection algorithms are proposed for general and dedicated MSR, CORDIC structures.
Abstract: Mixed-scaling-rotation (MSR) coordinate rotation digital computer (CORDIC) is an attractive approach to synthesizing complex rotators. This paper presents the fixed-point error analysis and parameter selections of MSR-CORDIC with applications to the fast Fourier transform (FFT). First, the fixed-point mean squared error of the MSR-CORDIC is analyzed by considering both the angle approximation error and signal round-off error incurred in the finite precision arithmetic. The signal to quantization noise ratio (SQNR) of the output of the FFT synthesized using MSR-CORDIC is thereafter estimated. Based on these analyses, two different parameter selection algorithms of MSR-CORDIC are proposed for general and dedicated MSR-CORDIC structures. The proposed algorithms minimize the number of adders and word-length when the SQNR of the FFT output is constrained. Design examples show that the FFT designed by the proposed method exhibits a lower hardware complexity than existing methods.

33 citations

Journal ArticleDOI
TL;DR: A novel algorithm based on discrete Fourier transform to estimate the frequency of power system frequency that is immune to inter-harmonics as well as harmonics; it has simple and easy implementation; and it has good performance both in steady and dynamic states.
Abstract: A novel algorithm based on discrete Fourier transform (DFT) to estimate the frequency of power system is proposed. The algorithm that we called transformed discrete Fourier transform (TDFT) involves transforming consecutive points of DFT of voltage signals to reduce the leakage components. The algorithm has the following merits: It is immune to inter-harmonics as well as harmonics; it has simple and easy implementation; and it has good performance both in steady and dynamic states. What is more, it can keep high precision in a very wide frequency deviation range, for example, 40-60 Hz. Simulation experiments validate this algorithm can track power system frequency precisely.

33 citations

Proceedings ArticleDOI
03 Nov 2003
TL;DR: This paper presents an FFT approximation technique suitable for on-chip spectral BIST signal generation and analysis and shows that the noise produced by the approximation technique is under 24.74 dB for a 256 point FFT with a 32 point approximate kernel.
Abstract: Signal generation and analysis are an important part of BIST for analog and mixed-signal systems. An accurate analysis of the spectral content of signals produced by analog components can be accomplished with a digital implementation of a fast Fourier transform (FFT) algorithm. In the past, size and speed have limited the application of such a technique to off-chip test equipment or DSP chips (primarily due to the number of multiplication operations). In this paper, we present an FFT approximation technique suitable for on-chip spectral BIST signal generation and analysis. For signal generation, we show that the noise produced by the approximation technique is under 24.74 dB for a 256 point FFT with a 32 point approximate kernel. For signal analysis, we show that the instantaneous dynamic range (IDR) for the approximation technique is under 21.80 dB for a 256 point FFT with a 32 point approximate kernel. Our techniques have been implemented and demonstrated on a Xilinx Virtex-II FPGA using an off-chip ADC and DAC, and we are currently implementing the technique on an ASIC using a 0.13 /spl mu/m SiGe process for 2-16 GHz applications.

32 citations

Journal ArticleDOI
TL;DR: The implementation results show that the proposed 128‐point mixed‐radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128‐ point FFT architectures.
Abstract: In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultrawideband systems. The proposed 128-point FFT processor employs both a modified radix-2 4 algorithm and a radix-2 3 algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 µm CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

32 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20235
202224
20211
20188
201757
201692