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Prime-factor FFT algorithm

About: Prime-factor FFT algorithm is a research topic. Over the lifetime, 2346 publications have been published within this topic receiving 65147 citations. The topic is also known as: Prime Factor Algorithm.


Papers
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Journal ArticleDOI
01 Apr 1987
TL;DR: The computational method uses the sprit-radix algorithm which requires the least number of operations compared with other Hartley algorithms and is compared with those using the fast Fourier transform.
Abstract: The use of fast Hartley transform for fast discrete interpolation is considered. The computational method uses the sprit-radix algorithm which requires the least number of operations compared with other Hartley algorithms. Results from this method are compared with those using the fast Fourier transform.

27 citations

Proceedings Article
01 Jan 2009
TL;DR: The proposed method shows to be a good compromise between design flexibility and reduced computational effort and was used as a part of an effective melody extraction algorithm.
Abstract: In this paper we focus on multi-resolution spectral analysis algorithms for music signals based on the FFT. Two previously devised efficient algorithms (efficient constan tQ transform [1] and multiresolution FFT [2]) are reviewed and compared with a new proposal based on the IIR filtering of the FFT. Apart from its simplicity, the proposed method shows to be a good compromise between design flexibility and reduced computational effort. Additionall y, it was used as a part of an effective melody extraction algorithm.

27 citations

Proceedings ArticleDOI
03 Apr 1990
TL;DR: The problem of comparing different algorithms for the execution of the fast Fourier transform (FFT) is considered by using the necessary number of instruction cycles for an FFT implementation on different digital signal processors (DSPs) as a measure.
Abstract: The problem of comparing different algorithms for the execution of the fast Fourier transform (FFT) is considered. Instead of counting the required arithmetic operations, the necessary number of instruction cycles for an FFT implementation on different digital signal processors (DSPs) is used as a measure. It turns out that this more practical figure of merit yields a rather different valuation of the algorithms. Furthermore, a method to halve the table size for the radix-2 twiddle factors is described. Some new FFT programs for execution on DSPs are compared with programs provided by the manufacturers. >

27 citations

Journal ArticleDOI
TL;DR: A parallel architecture especially designed for a synthetic-aperture-radar (SAR) processing algorithm based on an appropriate two-dimensional fast Fourier transform (FFT) code is presented, allowing drastic reduction of the processing time, preserving elaboration accuracy and flexibility.
Abstract: A parallel architecture especially designed for a synthetic-aperture-radar (SAR) processing algorithm based on an appropriate two-dimensional fast Fourier transform (FFT) code is presented. The algorithm is briefly summarized, and the FFT code is given for the one-dimensional case, although all results can be immediately generalized to the double FFT. The computer architecture, which consists of a toroidal net with transputers on each node, is described. Parametric expressions for the computational time of the net versus the number of nodes are derived. The architecture allows drastic reduction of the processing time, preserving elaboration accuracy and flexibility. >

27 citations

Journal ArticleDOI
TL;DR: A unified hardware architecture that can be reconfigured to calculate 2, 3, 4, 5, or 7-point DFTs is presented and the processing element finds potential use in memory-based FFTs, where non-power-of-two sizes are required such as in DMB-T.
Abstract: A unified hardware architecture that can be reconfigured to calculate 2, 3, 4, 5, or 7-point DFTs is presented. The architecture is based on the Winograd Fourier transform algorithm and the complexity is equal to a 7-point DFT in terms of adders/subtractors and multipliers plus only seven multiplexers introduced to enable reconfigurability. The processing element finds potential use in memory-based FFTs, where non-power-of-two sizes are required such as in DMB-T.

27 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20235
202224
20211
20188
201757
201692