Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Integrated circuit yield statistics

Abstract: The random failure statistics for the yield of mass-produced semiconductor integrated circuits are derived by considering defect and fault formation during the manufacturing process. This approach allows the development of a yield theory that includes many models that have been used previously and also results in a practical control model for integrated circuit manufacturing. Some simpler formulations of yield theory that have been described in the literature are compared to the model. Application of the model to yield management are discussed and examples given.

A wafer-scale 3-D circuit integration technology

Abstract: The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 times 1024 visible imager with an 8-mum pixel pitch, and a 64 times 64 Geiger-mode laser radar chip are described

Process and temperature compensation in a 7-MHz CMOS clock oscillator

Abstract: This paper reports on the design and characterization of a process, temperature and supply compensation technique for a 7-MHz clock oscillator in a 0.25-/spl mu/m, two-poly five-metal (2P5M) CMOS process. Measurements made across a temperature range of -40/spl deg/C to 125/spl deg/C and 94 samples collected over four fabrication runs indicate a worst case combined variation of /spl plusmn/2.6% (with process, temperature and supply). No trimming was performed on any of these samples. The oscillation frequencies of 95% of the samples were found to fall within /spl plusmn/0.5% of the mean frequency and the standard deviation was 9.3 kHz. The variation of frequency with power supply was /spl plusmn/0.31% for a supply voltage range of 2.4-2.75 V. The clock generator is based on a three-stage differential ring oscillator. The variation of the frequency of the oscillator with temperature and process has been discussed and an adaptive biasing scheme incorporating a unique combination of a process corner sensing scheme and a temperature compensating network is developed. The biasing circuit changes the control voltage of the differential ring oscillator to maintain a constant frequency. A comparator included at the output stage ensures rail-to-rail swing. The oscillator is intended to serve as a start-up clock for micro-controller applications.

Process and Temperature Compensation in a 7-MHz

Abstract: This paper reports on the design and characterization of a process, temperature and supply compensation technique for a 7-MHz clock oscillator in a 0.25- m, two-poly five-metal (2P5M) CMOS process. Measurements made across a temperature range of 40 C to 125 C and 94 samples collected over four fabrica- tion runs indicate a worst case combined variation of 2.6% (with process, temperature and supply). No trimming was performed on any of these samples. The oscillation frequencies of 95% of the sam- ples were found to fall within 0.5% of the mean frequency and the standard deviation was 9.3 kHz. The variation of frequency with power supply was 0.31% for a supply voltage range of 2.4-2.75 V. The clock generator is based on a three-stage differential ring oscillator. The variation of the frequency of the oscillator with tem- perature and process has been discussed and an adaptive biasing scheme incorporating a unique combination of a process corner sensing scheme and a temperature compensating network is de- veloped. The biasing circuit changes the control voltage of the dif- ferential ring oscillator to maintain a constant frequency. A com- parator included at the output stage ensures rail-to-rail swing. The oscillator is intended to serve as a start-up clock for micro-con- troller applications.

Systems, methods, and apparatus to perform statistical static timing analysis

Abstract: A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners using a static timing analysis module, and estimating performance of the circuit at a predetermined confidence level based on results of the statistical analysis during an automated design flow of the circuit without using libraries at the predetermined confidence level.