Showing papers on "Process corners published in 1983"

Integrated circuit yield statistics

Abstract: The random failure statistics for the yield of mass-produced semiconductor integrated circuits are derived by considering defect and fault formation during the manufacturing process. This approach allows the development of a yield theory that includes many models that have been used previously and also results in a practical control model for integrated circuit manufacturing. Some simpler formulations of yield theory that have been described in the literature are compared to the model. Application of the model to yield management are discussed and examples given.

Semiconductor integrated circuit which allows adjustment of circuit characteristics in accordance with storage data of nonvolatile memory element

Abstract: The invention provides a semiconductor integrated circuit, characteristics of which can be adjusted in accordance with storage data in a nonvolatile memory element. The semiconductor integrated circuit has a main semiconductor circuit having MOS transistors, and an adjusting circuit connected to the main semiconductor circuit so as to change the circuit characteristics of the main semiconductor circuit as needed. The adjusting circuit has MOS transistors and a plurality of fuse elements. The adjusting circuit causes a given fuse element to selectively disconnect in accordance with an input signal and generates at least one adjusting signal to adjust the circuit characteristics of the main semiconductor circuit.

Monolithically integrated semiconductor circuit with transistors

Abstract: Monolithically integrated semiconductor circuit with transistors, the semiconductor circuit proper having elements thereof formed on the front side of a semiconductor chip, the latter also having at the surface thereof two supply terminals actable upon by a respective supply potential and connected, on the one hand, to the elements of the semiconductor circuit proper and, on the other hand, to an additional circuit part for generating a substrate bias applied to a substrate region occupying the rear side of the semiconductor chip and, respectively, to at least one semiconductor zone belonging to the semiconductor circuit proper and to a gate electrode on the front side of the semiconductor chip which controls the semiconductor zone and is insulated therefrom, including a series connection of the substrate bias generator and the semiconductor circuit proper dividing a voltage present at the two supply terminals of the semiconductor chip in a manner that a reference potential required for the semiconductor circuit proper is produced.

Method of aligning a mask and a wafer for manufacturing semiconductor circuit elements

Abstract: This specification discloses a method of aligning a mask and a wafer for manufacturing semiconductor circuit elements into a predetermined positional relationship. The method comprises two steps. In a first step, the mask and wafer are aligned by the use of relatively large alignment marks provided on the mask and wafer. In a second step, the mask and wafer are aligned by using relatively small key patterns provided on the mask and wafer and having substantially no positional deviation with respect to actual element (circuit) patterns.