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Showing papers on "Process corners published in 1997"


Patent
Yukihito Oowaki1, Tsuneaki Fuse1
23 Oct 1997
TL;DR: In this paper, a stable high-speed integrated circuit driven by a wide range of low voltages and consuming low power is presented, where signals are applied to its gate and body for forming a circuit block which comprises a transistor network and at least one buffer circuit.
Abstract: A stable high-speed integrated circuit driven by a wide range of low voltages and consuming low power. A MOSFET is used wherein signals are applied to its gate and body for forming a circuit block which comprises a transistor network and at least one buffer circuit. Each buffer circuit has at least two configurations. A plurality of circuit blocks are formed on the same IC chip. Any of the configurations of the buffer circuit may be selected according to the magnitude of the capacitance of the load driven by the circuit block.

62 citations


Patent
12 Mar 1997
TL;DR: In this article, the authors proposed a method to control transistor drive current by controllably varying light exposure across a semiconductor substrate wafer based on an integrated circuit parameter such as gate oxide thickness, rapid temperature annealing (RTA) temperature, polyetch bias and the like.
Abstract: Transistor drive current is controlled by controllably varying light exposure across a semiconductor substrate wafer based on an integrated circuit parameter. Integrated circuit parameters upon which the light exposure is varied include gate oxide thickness, rapid temperature annealing (RTA) temperature, polyetch bias and the like.

47 citations


Patent
21 Oct 1997
TL;DR: In this article, the scribe lanes are processed during wafer fabrication to facilitate the flow of current to and from the wafer substrate through the scriber lanes during integrated circuit fabrication and reduce current flow through integrated circuit components.
Abstract: Charging damage to integrated circuits during ion implantation and plasma processing of integrated circuit die in a semiconductor wafer is reduced by processing scribe lanes during wafer fabrication to facilitate the flow of current to and from the wafer substrate through the scribe lanes during integrated circuit fabrication and reduce current flow through integrated circuit components.

13 citations


Patent
Asai Mikio1, Ryoichi Takagi1
15 Dec 1997
TL;DR: In this paper, the authors present a test device capable of solving a problem of a conventional one in that in the resistance measurement of a semiconductor integrated circuit it was difficult for the measurement error due to contact resistance or wiring resistance to be limited within a desired amount.
Abstract: A semiconductor test device capable of solving a problem of a conventional one in that in the resistance measurement of a semiconductor integrated circuit it was difficult for the measurement error due to contact resistance or wiring resistance to be limited within a desired amount. The present semiconductor test device includes, in a semiconductor integrated circuit having a first semiconductor switch functioning as a pullup resistor and a second semiconductor switch functioning as a pulldown resistor, a measuring circuit for bringing the first and second semiconductor switches into conduction at the same time in response to a signal fed from a control circuit, a voltage measuring circuit for measuring the voltage at a connecting point between the two semiconductor switches, and a current measuring circuit for measuring a through current flowing through the two semiconductor switches.

10 citations


Proceedings ArticleDOI
08 Sep 1997
TL;DR: An EEPROM development case is shown, which has been done on a transient circuit simulation level from the beginning, and a precise unified EEPRom cell model was developed describing all characteristics with surface potentials dependent on technological parameter values.
Abstract: Circuit simulation enters into a new stage of enhanced importance. From the conventional circuit simulator for circuit design an active tool for concurrent engineering is emerging, which allows to integrate technology, device and circuit development in parallel. We will show here an EEPROM development case, which has been done on a transient circuit simulation level from the beginning. A precise unified EEPROM cell model was developed describing all characteristics with surface potentials dependent on technological parameter values. This new model enabled us to realize the requested circuitry goals from the first wafer run.

5 citations


Proceedings ArticleDOI
07 Dec 1997
TL;DR: In this article, the authors describe a methodology to reduce the time and cost of developing deep sub-micron semiconductor manufacturing technology, which consists of following the components: compact models for device performance and reliability, compact model for process modules, and synthesis algorithms that allow the rapid exploration of large design spaces to identify all device and process flow designs that meet the device specifications.
Abstract: This paper describes a methodology to reduce the time and cost of developing deep sub-micron semiconductor manufacturing technology. The methodology consists of following the components: compact models for device performance and reliability, compact models for process modules, and synthesis algorithms that allow the rapid exploration of large design spaces to identify all device and process flow designs that meet the device specifications. This approach is illustrated by applying it to the design of CMOS gate shrinks from 0.35 /spl mu/m to 0.29 /spl mu/m drawn poly gate length. The synthesized devices were manufactured, meeting all performance and reliability requirements in the first silicon run.

4 citations


Proceedings ArticleDOI
08 Jun 1997
TL;DR: This work presents a methodology to study the influence of the interconnect variation on circuit performance, and parameterized interconnect modeling technology is introduced, and a ring oscillator circuit with interconnect dominant loading is studied.
Abstract: Deep submicron technology makes interconnect one of the main factors determining the circuit performance. Previous work shows that interconnect parameters exhibit a significant amount of spatial variation. In this work, we present a methodology to study the influence of the interconnect variation on circuit performance. Parameterized interconnect modeling technology is introduced, and a ring oscillator circuit with interconnect dominant loading is studied.

4 citations


Patent
23 Oct 1997
TL;DR: In this article, the authors proposed a method to control the temperature of the semiconductor wafer of a semiconductor integrated circuit element to an optimum temperature, at the time of inspecting the circut element.
Abstract: PROBLEM TO BE SOLVED: To easily and surely control the temperature of the semiconductor wafer of a semiconductor integrated circuit element to an optimum temperature, at the time of inspecting the circut element SOLUTION: Diode elements, which detect the temperature of a semiconductor wafer 12 on which semiconductor integrated circuit elements 21 to be inspected are formed and are constituted by connected impurity-diffused region having different conductivities, are provided in advance to TEGs 24 for managing process on the wafer 12 Then, after the wafer 12 has been heated to a prescribed temperature, burn-in is performed by inputting a signal having a prescribed input pattern During inspections, the electrical signals outputted from the diode elements are measured, and the temperature of the wafer 12 is controlled to a prescribed value based on the measuring results COPYRIGHT: (C)1999,JPO

3 citations


01 Jan 1997
TL;DR: In this paper, a 5-bit 2.5V temperature sensor implemented in a 0.35pm CMOS technology is described, which is fully differential and based on the PTAT voltage difference between two diodes, yet it does not require a bandga reference.
Abstract: A 5-bit 2.5V temperature sensor implemented in a 0.35pm CMOS technology is described. The sensor is fully differential and based on the PTAT voltage difference between 2 diodes, yet it does not require a bandga reference. The resolution is 4OC for a temperature range of 0 C to 128OC. The offset error is 12OC over the process corners. The integral nonlinearity is below 1 LSB and the differential nonlinearity is less than 1/2 LSB. The total area of the sensor is 0.192 mm2 and the maximum power dissipation is 1OmW at 2.5V.

1 citations


Patent
08 Dec 1997
TL;DR: In this article, a high aspect ratio integrated circuit device (HARIMA) is presented, which has a length greater than three times its width and a width greater than two times its length.
Abstract: An integrated circuit device package (10) including a high aspect ratio integrated circuit device (12) is disclosed. The device (12) has a length (L1) than is greater than three times its width (L2). The device includes a plurality of circuit functional blocks (14), each having a plurality of integrated circuit components and bond pads (16) for the input and output of signals. In one embodiment, the circuit functional blocks (14) are aligned in parallel to form a row of circuit functional blocks. The high aspect ratio integrated circuit device (12) requires less wafer area than a comparable low aspect ratio device, thus allowing more devices to be made from a single semiconductor wafer at a lower cost per device. Moreover, the disclosed method for producing a high aspect ratio integrated circuit device package (10) minimizes the risk of cracking the high aspect ratio integrated circuit device (12) during the packaging process.