Showing papers on "Process corners published in 1998"

Process variations and their impact on circuit operation

Abstract: The statistical variations in electrical parameters, such as transistor gain factors and interconnect resistances, due to variations in the manufacturing process are studied using data obtained from a 0.8 /spl mu/m CMOS process. The impact of these variations and correlations on circuit operation is illustrated. Examples show that circuit delay can increase from the mean by about 100% due to crosstalk effects aggravated by process variations. Case studies emphasize the need for a tighter coupling between fabrication and circuit design and the need for new design corners based on process information.

Method and apparatus for a wafer level system

Abstract: An improved wafer scale integrated circuit is described which includes non-contact power and data transmission coupling. Wireless power and data coupling reduces the mechanical stresses and strains on the wafer, and makes better use of the wafer area. An additional benefit comes from allowing better heat transfer management. In one embodiment, power is provided by inductive coupling. Data flow into and out of the wafer is accomplished optically, using optical detectors to receive and light emitting diodes to transmit. Multiple devices are integrated onto the semiconductor wafer. Systems may be incorporated using the traditional die sites. Connections between systems are made in the space between die sites.

Method and apparatus for detecting process sensitivity to integrated circuit layout using wafer to wafer defect inspection device

Abstract: A method and apparatus for detecting random layout structures sensitive to process induced pattern errors in semiconductor device manufacturing applies a first manufacturing process to a first wafer containing semiconductor devices. A second manufacturing process is applied to a second wafer containing semiconductor devices. The second manufacturing process is similar to, but different from the first manufacturing process. The first and second wafers are compared by image subtraction to detect systematic pattern defects in the semiconductor devices of one of the first and second wafers. After differences are detected, the layout is examined to determine whether the difference represents a defect. If so, the design rules of the layout can be changed to accommodate a wider process variation and improve processing yield.

Method for photo composition of large area integrated circuits

Abstract: A method for forming very large scale integrated circuit devices employs a reticle having plural discrete image fields which may be respectively blocked off and exposed to form patterns on an integrated circuit wafer substrate. The division of the circuit pattern to be imaged into separate image fields is based on repeatable horizontal, vertical and two dimensional structures in the overall circuit pattern of the integrated circuit. By repeatedly exposing image fields corresponding to repeatable structures, the size of the integrated circuit device may be scaled without requiring similar scaling of the reticle itself. Efficient exposure of an entire wafer may be provided by having image fields including circuit patterns which include the scribe lanes which separate the integrated circuits on the wafer to be imaged.

A method for minimizing the critical dimension growth of a feature on a semiconductor wafer

Abstract: A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor (20) and controlling the temperature of the wafer (26) by controlling the pressure of the gas contacting the backside of the wafer (26) and/or providing a heat source (56) such as for example in the chuck (46) or electrode (28) associated with the wafer (26) in order to heat the wafer (26).

Semiconductor integrated circuit device capable of achieving reductions in chip area and consumption power

Abstract: This is provided a dual-surface mounting type semiconductor integrated circuit device capable of achieving reductions in chip area and consumption power. In the dual-surface mounting type semiconductor integrated circuit device, a specified circuit for implementing a function common to integrated circuit chips and mounted on both surfaces of a chip mounting section of a lead frame is provided only for the integrated circuit chip of one surface, and an output signal of the specified circuit provided only for the integrated circuit chip of this one surface is transmitted to the integrated circuit chip of the other surface via bonding wires and an internal lead.

Design methodology for on-chip interconnects

Abstract: A design methodology for on-chip interconnects which utilizes fast circuit simulator techniques to control signal coupling and transition rate degradation is described. CMOS process technology trends and their effects on interconnect performance are discussed. Critical design parameter curves are used to optimize a set of wire geometries that satisfies the electrical constraints for high density chips.