Showing papers on "Process corners published in 2001"

Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same

Abstract: An integrated circuit and method for forming the same. The integrated circuit includes a semiconductor wafer with first and second surfaces. A functional circuit is formed on the first surface of the semiconductor wafer. Further, a metallization layer is formed outwardly from the first surface of the semiconductor wafer. The integrated circuit also includes at least one high aspect ratio via that extends through the layer of semiconductor material. This via provides a connection between a lead and the functional circuit.

Semiconductor manufacturing apparatus and method of processing semiconductor wafer using plasma, and wafer voltage probe

Abstract: A semiconductor manufacturing apparatus includes a unit for generating a plasma in a vacuum chamber, a wafer stage for holding a semiconductor wafer introduced into the vacuum chamber, a high frequency power supply for applying a high frequency voltage to the wafer stage, a wafer voltage probe for measuring a voltage of the semiconductor wafer at a rear surface of the semiconductor wafer, a current and voltage probe for measuring at least one of a voltage and a current applied to the wafer stage from the high frequency power supply, and a control portion. The control portion obtains an impedance from the semiconductor wafer to earth through the plasma on the basis of a voltage value of the semiconductor wafer measured by the wafer voltage probe, and a voltage value or a current value measured by the current and voltage probe, and performs a processing based on the obtained impedance.

Integrated on-chip process, temperature, and voltage sensor module

Abstract: An integrated on-chip process, temperature, and voltage sensor is provided. Further, a method to monitor a process corner, temperature, and voltage on a computer chip is provided. Further, an on-chip voltage monitor is provided. Further, a method to monitor a voltage on a section of a computer chip is provided. Further, an integrated testing module having voltage, temperature, and sensor components is provided.

Method for forming integrated circuits using high aspect ratio vias through a semiconductor wafer

Abstract: An integrated circuit and method for forming the same. The integrated circuit includes a semiconductor wafer with first and second surfaces. A functional circuit is formed on the first surface of the semiconductor wafer. Further, a metallization layer is formed outwardly from the first surface of the semiconductor wafer. The integrated circuit also includes at least one high aspect ratio via that extends through the layer of semiconductor material. This via provides a connection between a lead and the functional circuit.

A semiconductor integrated circuit and fabrication process having compensated structures to reduce manufacturing defects

Abstract: A semiconductor integrated circuit that includes thereon a flash memory and a plurality of MOS transistors using different power supply voltages is formed by a process in which a thermal oxidation process is applied to one of the device regions while covering the other device regions by an oxidation-resistant film.

Crosstalk noise verification in digital designs with interconnect process variations

Abstract: Interconnect parasitics are playing a significant role in design and analysis in deep sub-micron (DSM) technologies. Interconnect process variations could play a significant role in achieving predictable yield. Crosstalk noise is one of the increasingly important careabouts in DSM designs. In this paper, a practical method to analyze the crosstalk noise effects with interconnect process variations using corner-based approach is described. The results from application of this method on a large DSP design implemented in 0.18/spl mu/ technology is presented. Application of the proposed method resulted in detection of a new worst case interconnect process corner that was not included in the design methodology.

Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability

Abstract: We propose an efficient, test-circuit-based method to determine not only CMOS-device-parameter variations but to simultaneously separate intra-chip from inter-chip variations. The method is demonstrated by using a differential-amplifier stage with feedback coupling as the test-circuit and the drift-diffusion MOSFET model HiSIM for the circuit simulation. The result shows that the proposed test circuit, when constructed only with n-MOSFETs or p-MOSFETs, enables one to separate gate length and channel doping variations as well as their inter- and intra-chip magnitudes in a direct way.

Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation

Abstract: In power-constrained systems, the power efficiency of latches and flip-flops is pivotal. Characteristics of three selected latches and FFs were analyzed for their behavior under voltage scaling and different process corners in a 0.18 /spl mu/m CMOS technology. The relative performance amongst the latches/FFs was consistent across the different supply voltages. At low-voltage power-delay product was degraded by about 25%. Energy-delay-product was approximately doubled at low-voltage, for all latches/FFs over all process corners. This result was smaller in comparison to the ideal voltage scaling characteristics mainly because the effects of velocity saturation were less severe at low voltage. All three designs suffered more due to process variation under low-voltage conditions.

Method for producing semiconductor integrated circuit chip and semiconductor package using semiconductor integrated circuit chip

Abstract: PROBLEM TO BE SOLVED: To provide a method for producing a semiconductor integrated circuit chip having fine side face electrodes (fine pitch electrodes) in which occupation area of electrode pads for I/O signal (through electrodes) on the surface of the semiconductor integrated circuit chip can be reduced and the side face of the semiconductor integrated circuit chip can be utilized effectively. SOLUTION: When a semiconductor wafer 11 is separated individually (diced) into semiconductor integrated circuit chips, through holes 1 are made on the border line 8 of a semiconductor integrated circuit region 10 becoming the semiconductor integrated circuit chip and a scribe region 2 being cut out formed between the semiconductor integrated circuit regions 10, and through hole electrodes are formed in the through holes 1 such that they are exposed to the side face of the semiconductor integrated circuit chips at the time of dicing. COPYRIGHT: (C)2003,JPO

Method and device for analyzing electromagnetic wave interference, and method for manufacturing semiconductor device using them

Abstract: PROBLEM TO BE SOLVED: To reduce magnetic wave interferences, while maintaining increase in the scale and in speed of LSI. SOLUTION: A method for analyzing noise from the outside to a semiconductor integrated circuit comprises a process of extracting the impedance information of a power source wiring inside the semiconductor integrated circuit, as well as outside the semiconductor integrated circuit device; an equivalent circuit making process for making an equivalent circuit from the impedance information; and an analyzing process for supplying noise waveform from the outside as input information to the equivalent circuit and analyzes the effects of noise on the semiconductor integrated circuit. COPYRIGHT: (C)2006,JPO&NCIPI

Power semiconductor circuit device incorporating function monitoring circuit within power semiconductor control circuit

Abstract: The circuit device has a control circuit, a substrate and at least one power semiconductor (1), provided with contacts (10) on the side facing the substrate, coupled to electrically isolated conductive surfaces (18,33) of the substrate via at least 2 bonding wires (13,14). The control circuit incorporates a function monitoring circuit for the power semiconductor. An Independent claim for a method for monitoring a power semiconductor circuit device is also included.

Device and method for testing performance of silicon structures

Abstract: An integrated test circuit for a silicon on insulator circuit structure is formed on the same wafer as the circuit structure. The wafer includes an input circuit coupled to the silicon on insulator circuit structure which generates a drive signal for operating the silicon on insulator circuit structure and an output circuit which processes a response signal from the circuit structure to generate an output signal representing certain characteristics of the silicon on insulator circuit structure.

A 10-bit, 2.5-V, 40 M sample/s, pipelined analog-to-digital converter in 0.6-/spl mu/m CMOS

Abstract: A high-speed, low-voltage pipelined analog-to-digital converter is presented. It achieves 58 dB SNDR with full-scale Nyquist rate sinusoidal input and conversion rate of 40 MHz with a power supply of 2.25 V. A 1.5 bit per stage architecture is used for all the stages except the first one. The first stage employs more comparators to reduce the signal swing at the output of the stage, hence relaxes conditions on the op-amp transistor sizes in the subsequent stages. Simulation results have been checked with all process corners from -40/spl deg/C to +120/spl deg/C and /spl plusmn/15% variation in poly-poly capacitor sizes.

A 2.5 Gbit/s CMOS PLL for data/clock recovery without frequency divider

Abstract: A phase locked loop (PLL) design based on a new phase detector (PD) is presented It can be used as a part of data/clock recovery (DCR) systems targeting the applications of 2 Gbit/s-3 Gbit/s range Ethernet and optic fiber transceivers in current semiconductor processes A key component in the circuit is a new non-sequential PD that provides for very high speed operation Using TSMC 025 u CMOS process device models and the HSPICE simulator, results show that the PLL can operate at 25 GHz over process corners and a 0/spl deg/C to 100/spl deg/C temperature range Total power dissipation is 40 mW with a single 25 V power supply

Noise detector and semiconductor integrated circuit

Abstract: PROBLEM TO BE SOLVED: To detect noise generated in a semiconductor integrated circuit without bringing a probe directly in contact with a semiconductor integrated circuit even when an exclusive pad for detecting noise is removed. SOLUTION: An oscillator 2 composed of a ring oscillator or a voltage controlled oscillator is mounted on the semiconductor integrated circuit 1 having a digital circuit and an analog circuit, and a jitter value from the oscillator 2 is measured by a jitter measuring circuit 3, so that a substrate current generated due to the ON/OFF of the digital circuit can be caught. COPYRIGHT: (C)2003,JPO

Behavioral modeling for timing, noise, and signal integrity analysis

Abstract: I/O behavioral modeling in the form of IBIS models has gained wide acceptance in signal integrity analysis. While the IBIS model accurately represents the characteristics of the output pin at three fixed process corners, it does not model driver delay or account for variations in temperature, supply voltages, and input transition rate. In this paper, we present a behavioral modeling technique that captures driver delay for timing analysis, driver output characteristics for signal integrity, and pre-drive currents for noise and power grid analysis; all are functions of temperature, supply voltages, and input transition rate.

Advanced procedure to evaluate process performance at very low k1 based on device parameters linked to lithography and process data:II. Verification of cell layout based on integration of optical an

Abstract: This is an extension of our previous work where we discussed basic assumptions of device oriented process verification. Here, we propose an integrated procedure to verify the design of active devices and interconnections. It entails extraction of device, contact, and interconnect electrical performance based on optical simulation of layout geometries, including proximity correction features, combined with critical dimension (CD) variation and misalignment. A critical analysis, proposed in this work, made it possible to focus the simulation on the selected process corner options. We integrated multi-level optical and device simulation to verify dense layouts for deep sub- wavelength design rules in a six-transistor advanced memory cell.

Dynamic receiver biasing for inter-chip communication

Abstract: A noise cancellation circuit was designed to improve the performance of a single-ended source-synchronous I/O interface. Common-mode variations between the high-frequency data bits and the DC reference against which they are compared were nulled using negative feedback. The clock and its complement were filtered at the receiving chip to establish an average value, which corresponds to duty cycle. That value was amplified and fed back to correct the biasing of the I/O receivers in such a way that the clocks were received with 50% duty-cycle. The biasing is shared among all I/O receivers. A prototype was designed in the HP-14B CMOS process and demonstrated using a current-mode I/O receiver that was developed simultaneously. The power supply voltage was 2.5-V. Measured results indicated that the noise cancellation circuit improved the receiver's bandwidth improved by 12% (1020-Mb/s vs 910-Mb/s), and system's static power-supply rejection (between transmitter and receiver) improved by a factor of 3.75 (/spl Delta/V/sub DD/=750-mV vs/spl Delta/V/sub DD/=200-mV). A more I/O conventional interface was also implemented using this technique in a 0.18 /spl mu/m CMOS process. The simulation environment allowed for a direct comparison between a conventional voltage reference transmission scheme and the dynamic biasing technique given a mismatch in transmitter and receiver process corners, a 100 cm signal trace, and a 5% static power supply gradient between the two chips. Simulated results indicated that the use of dynamic biasing reduced the timing jitter in the received eye from 1.8 ns to 1.18 ns, for a 3.0 ns bit-time.

Semiconductor integrated circuit and method of compensating for device performance variations of semiconductor integrated circuit

Abstract: A semiconductor integrated circuit chip is divided into a plurality of regions each incorporating a performance variation compensating circuit. The performance variation compensating circuit supplies a power supply to a MOS FET in the region to compensate for threshold voltage variations.