Showing papers on "Process corners published in 2002"

Inspection system and inspection process for wafer with circuit using charged-particle beam

Abstract: In a method for inspecting positions and types of defects on wafers with circuit patterns in a semiconductor manufacturing process, inspection is made regardless of the types and materials of junctions of circuit patterns of the semiconductor devices, different kinds of defects being distinguished from one another. Further, electrification of the circuit pattern is prevented, and the area to be exposed to an electron beam is controlled evenly and at a desired voltage. During inspection of the positions and types of defects on a wafer using a charged-particle beam from a charged-particle source, an optical beam from an optical source as well as a charged-particle beam are applied to a junction of the circuit pattern of the wafer placed on a wafer holder. Thus, regardless of the types and materials of circuit patterns, a highly sensitive inspection is made according to contrasts in the defects of a captured image.

Explicit computation of performance as a function of process variation

Abstract: Each manufactured chip is a little bit different, and designers want as many as possible of these chips to work. Process variation is a function of many variables, as the width, thickness, and inter-layer thickness can vary independently for each layer on a chip, as can temperature and voltage. Currently designers cope with this by picking a few subsets of these conditions, called process corners, and analyzing at these conditions. However, it's easy to show this approach is both too conservative (the specified conditions will seldom occur) and not conservative enough (it misses errors that can occur due to process variation). We present a unified theory of process variation that includes inter-chip variation, intra-chip deterministic variation (such as caused by proximity effects and metal density), and intra-chip statistical variation. Using this mechanism, we can explicitly compute performance as a function of process variation. This allows us to compute less pessimistic timing numbers and address yield optimization in the design process.

Test circuit, semiconductor product wafer having the test circuit, and method of monitoring manufacturing process using the test circuit

Abstract: A test circuit and a method of monitoring a manufacturing process of a semiconductor integrated circuit using the test circuit are provided. The test circuit comprises elements to be tested; a selection circuit for sequentially selecting at least one of the elements at a time. The test circuit and pads used for testing the elements are placed within a scribe line on a semiconductor wafer.

Method and apparatus to estimate burn-in time by measurement of scribe-line devices, with stacking devices, and with common pads

Abstract: A method and apparatus for estimating burn-in time for integrated circuit die on a wafer employs a reliability testing structure placed in a scribe line area of a wafer to permit improved estimation of burn-in time for integrated circuit on a wafer. Each reliability testing structure has a plurality of evaluation device structures formed on the substrate. Groups of the evaluation device structures are stacked on the surface of the substrate. The device structures are created to permit evaluation of one of a plurality of failure mechanisms of the integrated circuit. A forcing input pad and a sensing output pad are connected through a selection circuit to at least one of the evaluation devices. The selection circuit selects which of the evaluation devices are to receive a stimulus and to transmit a response. The stimulus is activated and the substrate is then stressed. Each selected evaluation device structure is examined for failure and the hazard rate for each failure mechanism of the integrated circuit is determined and from the hazard rate the burn-in time for the integrated circuit is calculated.

Using scatterometry to obtain measurements of in circuit structures

Abstract: A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. Measurements are taken in accordance with scatterometry based techniques of repeating in circuit structures that evolve on a wafer as the wafer undergoes the fabrication process. The measurements can be employed to generate feed forward and/or feedback control data that can utilized to selectively adjust one or more fabrication components and/or operating parameters associated therewith to adapt the fabrication process. Additionally, the measurements can be employed in determining whether to discard the wafer or portions thereof based on a cost benefit analysis, for example. Directly measuring in circuit structures mitigates sacrificing valuable chip real estate as test grating structures may not need to be formed within the wafer, and also facilitates control over the elements that actually affect resulting chip performance.

Process monitor based keeper scheme for dynamic circuits

Abstract: An invention is disclosed for a process monitor based keeper scheme for dynamic circuits. A semiconductor die having a process monitor based keeper scheme of the embodiments of the present invention generally includes a plurality of dynamic circuits, each having an adaptive keeper circuit capable of being adjusted based on a bit code. In addition, a plurality of process monitors is included. Each process monitor is disposed within a corresponding die block, which defines a local area of the die. The process monitors are capable of detecting process corner data for the corresponding die block. In communication with each process monitor and the plurality of dynamic circuits is a test processor unit. The test processor unit obtains process corner data for each die block from the process monitor disposed within the die block, and provides a bit code based on the process corner data to the dynamic circuits disposed within the die block.

Wafer with additional circuit parts in the kerf area for testing integrated circuits on the wafer

Abstract: Integrated circuits are tested on the wafer level through an additional circuit part that is electrically connected via at least one connecting line with the associated integrated circuit. The additional circuit part is integrated into an interspace between the integrated circuits of the wafer. Functions of the integrated circuit can be controlled via the connecting line. For example, in the case of a memory module such as a DRAM, internal voltages and/or currents of the integrated circuit can advantageously be measured even on internal lines which are otherwise only accessible with difficulty. Following the wafer-level testing and dicing of the integrated circuits into individual chips, the additional circuit part becomes unusable.

Critical dimension statistical process control in semiconductor fabrication

Abstract: The current invention provides a method for analyzing process variations that occur during integrated circuit fabrication. Critical dimension data is collected for each layer of the integrated circuit fabrication process for a period of time and a shift indicator that indicates variation in the critical dimension data for each layer of the integrated circuit fabrication process is calculated. A machine drift significance indicator is also calculated for each machine used in each layer of the integrated circuit fabrication process, and a maximum shift of mean value for each layer of the integrated circuit fabrication process is defined. The shift indicator, the maximum shift of mean value and the machine drift significance indicator are used to determine at least one likely cause of variation in critical dimension for each layer of the integrated circuit fabrication process.

Statistical methods for the determination of process corners

Abstract: Presents a statistical method to determine the variation of the production process of MOS transistors by finding the wafers that have parameter values on the boundary of the distribution. For the selection of the wafers a location depth method is used. Since it would be too time-consuming to determine the SPICE parameters for all the wafers and compute the boundary wafers in the SPICE domain, we use a different approach. We compute the boundary wafers based on production control parameters and then we transform the production control parameter values to SPICE parameter values. With the SPICE parameter values obtained in this way the circuit simulation is performed and since we use the data of the boundary wafers, we cover the variation of the production process within a certain time period. The applied scheme proves to describe the performance variation of analog/mixed-signal designs very accurately with a small number of simulations. For validation purposes circuit simulations and measurements of benchmark circuits are compared. The statistical methods can easily be integrated into a mixed-signal design environment.

A 3.3-V 18-bit digital audio Sigma-Delta modulator in 0.6-/spl mu/m CMOS

Abstract: This paper presents a 3.3-V, 18-bit Sigma-Delta modulator for digital audio, which has been simulated in a 0.6 /spl mu/m double poly, triple metal CMOS process using poly-poly capacitors in all process corners and considering /spl plusmn/ 10 % power supply and -40/spl deg/C to 85/spl deg/C temperature ranges. The integral gain coefficients of a 2-2 cascaded modulator have been developed for achieving higher overload level factor that is needed for high-resolution noise limited performance modulators. Simulation results give SNDR of 111 dB and 110 dB in typical and worst case, respectively with considering of the circuit noise.

Semiconductor wafer for in-process testing an integrated circuit and corresponding manufacturing method

Abstract: A semiconductor wafer configured for in-process testing of integrated circuitry fabricated thereon. At least two die are separated by a scribe area, and each of the die has at least one complementary metal oxide silicon (CMOS) static random access memory (SRAM) array embedded therein among mixed-signal CMOS circuitry. The mixed-signal CMOS circuitry includes devices with larger feature sizes compared to similar devices of the embedded SRAM array. A first process control monitor (PCM) testline is included, which has a first layout corresponding to the mixed-signal CMOS circuitry. Additionally, a second PCM testline is included, which has a second layout corresponding to the embedded SRAM arrays. The first and second PCM testlines are formed in the scribe area.

A 2.5-V 10-bit 40-MS/S double sampling pipeline A/D converter

Abstract: This paper presents a 10-bit pipeline ADC using double sampling technique to achieve a conversion rate of 40 MS/s at 2.5-V supply. The opamps are two-stage with folded-cascode as the first stage and feature techniques such as common-mode stabilized active load, cross-coupled cascode connection, and close-loop poles placement. MOS switches are driven by bootstrapping circuits that do not subject the devices to large, terminal voltages. The circuit layout is being completed and the chip will be fabricated in a 0.5-/spl mu/m CMOS technology. Simulation results have been checked for all process corners and including the effect of 3/spl sigma/ capacitor mismatch, comparator offset, 10% variation in poly-poly capacitor size and temperature varying from 0/spl deg/C to 70/spl deg/C. The results show that the converter has differential nonlinearity (DNL) of less than 0.4LSB and achieves 59.1 dB SNDR for 19.9 MHz sinusoidal inputs. Power consumption is estimated at 30.5 mW.

A high-speed, current-steering digital-to-analog converter in 0.6-/spl mu/m CMOS

Abstract: A 10-bit, current-steering, high-speed CMOS D/A converter is presented using a delay technique to increase the speed of the converter Simulation results show that the spurious-free-dynamic-range (SFDR) is better than 62 dB for sampling frequency up to 400 MSample/s and signals from DC to Nyquist Monte-Carlo simulations show that differential non-linearity (DNL) and integral non-linearity (INL) are better than 003 least significant bit (LSB) and 024 LSB, respectively The estimated INL-yield is 997% and the design is based on it The converter dissipates less than 250 mW from a 3 V power supply when operating at 400 MHz The circuit has been designed in a standard 06 /spl mu/m-CMOS process The results have been checked with all process corners from -40/spl deg/C to 85/spl deg/C and power supply from 27 V to 33 V