Showing papers on "Process corners published in 2004"

Process and environmental variation impacts on ASIC timing

Abstract: With each semiconductor process node, the impacts on performance of environmental and semiconductor process variations become a larger portion of the cycle time of the product. Simple guard-banding for these effects leads to increased product development times and uncompetitive products. In addition, traditional static timing methodologies are unable to cope with the large number of permutations of process, voltage, and temperature corners created by these independent sources of variation. In this paper we will discuss the sources of variation; by introducing the concepts of systematic inter-die variation, systematic intra-die variation and intra-die random variation. We will show that by treating these forms of variations differently, we can achieve design closure with less guard-banding than traditional methods.

High performance asynchronous ASIC back-end design flow using single-track full-buffer standard cells

Abstract: This work presents a back-end design flow for high performance asynchronous ASICs using single-track full-buffer (STFB) standard cells and industry standard CAD tools to perform schematic capture, simulation, layout, placement and routing. This flow is demonstrated and evaluated on a 64-bit asynchronous prefix adder and its test circuitry. The STFB standard cells provide low latency and fast cycle-times at the expense of some timing assumptions. This paper demonstrates that, by controlling top-block sizes and/or wire length within the place & route flow, ultra-high-performance circuits can be automatically designed. In particular, in the TSMC 0.25/spl mu/m process our post-layout STFB standard-cell 64-bit asynchronous prefix adder requires 0.96 mm/sup 2/, offers a latency of 2.1 ns, has a throughput of 1.4 GHz, and operates at five process corners as well as a wide-range of temperatures and voltages.

Technique for evaluating a fabrication of a semiconductor component and wafer

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

A process, voltage, and temperature compensated CMOS constant current reference

Abstract: In this paper, a CMOS constant current reference over PVT (process, voltage and temperature) variations is presented. The drain current of a MOS device gives the reference current, which is compensated for process variations by exploiting the physical relationship between K'(/spl mu/C/sub ox/) and V/sub T/ across various process corners. It is also compensated for power supply and temperature variations by a PTAT voltage reference, which aids in the generation of the reference current. In order to prove the proposed concept, simulation results from 0.25 /spl mu/m, 0.18 /spl mu/m, 0.13 /spl mu/m, and 90 nm CMOS processes are presented.

Semiconductor chip singulation method

Abstract: A method to singulate a circuit die from an integrated circuit wafer is achieved. The method comprises providing an integrated circuit wafer containing a circuit die. The integrated circuit wafer is cut through by performing a single, continuous cut around the perimeter of the circuit die to thereby singulate the circuit die.

Semiconductor integrated circuit apparatus, measurement result management system, and management server

Abstract: A semiconductor integrated circuit apparatus, and more particularly a technology for measuring and managing a physical amount of factors that exert an influence upon an operation of a semiconductor integrated circuit is provided; more particularly, a semiconductor integrated circuit that is an object of measurement, and a measurement circuit which measures a physical factor that exerts an influence upon the actual operation of the semiconductor integrated circuit, such as jitter or noise jitter, and noise of this semiconductor integrated circuit are provided on an identical chip; also, a measurement result of the measurement circuit of the present invention is analyzed, and is fed back to a circuit for adjusting the semiconductor integrated circuit that is the object of measurement.

High density integrated circuit package architecture

Abstract: This invention relates to a high density architecture for an integrated circuit package (10) in which a plurality of circuit communication wafers (12) are disposed in a stack with a plurality of cooling plates (14) between them, and wherein circuit communication between the communication wafers (12) is provided from wafer to wafer through the cooling plates (14). In addition, the communication wafers (12) may have integrated circuit chips (18) deposited on both sides of the wafer, and chip-to-chip communication may be provided from one surface of the wafer to another through the wafer. The resulting integrated circuit package may have any desired geometrical shape and will permit heat exchange, power and data exchange to occur in three generally mutually orthogonal directions through the package.

Built-in current sensor for /spl Delta/I/sub DDQ/ testing

Abstract: This paper presents the implementation of a built-in current sensor for /spl Delta/I/sub DDQ/ testing In contrast to conventional built-in current monitors, this implementation has three distinctive features: 1) built-in self-calibration to the process corner in which the circuit under test was fabricated; 2) digital encoding of the quiescent current of the circuit under test for robustness purposes; and 3) enabling versatile testing strategy through the implementation of two advanced /spl Delta/I/sub DDQ/ testing algorithms The monitor has been manufactured in a 018-/spl mu/m CMOS technology and it is based on the principle of disconnecting the device under test from the power supply during the testing phase The monitor has a resolution of 1 /spl mu/A for a background current less than 100 /spl mu/A or 1% of background currents over 100 /spl mu/A to a total of 1-mA full scale The sensor operates at a maximum clock speed of 250 MHz The quiescent current is indirectly determined by counting a number of clock pulses which occur during the time the voltage at the disconnected node drops below a reference voltage value Basically, at the end of the count period, the counted value is inversely proportional to the quiescent current of the device under test Then, a /spl Delta/I/sub DDQ/ unit processes the counted number and the outcome is compared with a reference number to determine whether a defect exists in the device under test Accuracy is improved by adjusting the value of the reference number and the frequency of the clock signal depending upon the particular process corner of the circuit under test The monitor has been verified in a test chip consisting of one "DSP-like" circuit of about 250,000 transistors Experimental results prove the usefulness of our approach as a quick and effective means for detecting defects

SPICE modeling of process variation using location depth corner models

Abstract: For robust designs, the influence of process variations has to be considered during circuit simulation. We propose a nonparametric statistical method to find sets of simulation parameters that cover the process spread with a minimum number of simulation runs. Process corners are determined from e-test parameter vectors using a location depth algorithm. The e-test corner vectors are then transformed to SPICE parameter vectors by a linear mapping. A special corner extension algorithm makes the resulting simulation setup robust against moderate process shifts while preserving the underlying correlation structure. To be applicable in a production and circuit design environment, the models are integrated into an automated model generation flow for usage within a design-framework. The statistical methods are validated for analog/mixed-signal benchmark circuits.

Worst-case circuit delay taking into account power supply variations

Abstract: Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low or high. This analysis may not give the true maximum delay of a circuit because it neglects the possible mismatch between drivers and loads. We propose a new approach for timing analysis in which we first identify the critical path(s) of a circuit using a power-supply-aware timing model. Given these critical paths, we then take into account how the power nodes of the gates on the critical path are connected to the power grid, and re-analyze for the worst-case time delay. This re-analysis is posed as an optimization problem where the complete operation of the entire circuit is abstracted in terms of current constraints. We present our technique and report on the implementation results using benchmark circuits tied to a number of test-case power grids.

Semiconductor integrated circuit testing device and method

Abstract: A plurality of resistors is connected to a plurality of output terminals of a semiconductor integrated circuit, respectively, and a predetermined voltage is applied to the plurality of resistors. Also, a predetermined operation pattern signal used to test functions of the semiconductor integrated circuit is input to a plurality of input terminals of the semiconductor integrated circuit. Thus, a total sum of amounts of currents caused to flow through the plurality of resistors, respectively, is measured. The total sum of amounts of currents thus measured is compared with a normal value of a total sum of amounts of currents which are measured in a non-defective sample which is used instead of the semiconductor integrated circuit and is verified in advance to normally operate. It is judged based on the comparison results whether or not the semiconductor integrated circuit is normal. As a result, whether or not the semiconductor integrated circuit is a non-defective or a defective can be simply judged without performing logic simulation and failure simulation.

Semiconductor integrated circuit device having an ESD protection unit

Abstract: A semiconductor integrated circuit device includes a semiconductor integrated circuit formed in a semiconductor chip, and a switching element that is formed in the semiconductor chip and has a current path whose one end and the other end are both connected to the semiconductor integrated circuit The switching element receives a control signal produced by a control circuit and causes a current to flow from the one end to the other end of the current path by a bipolar operation The semiconductor integrated circuit device further includes the control circuit that is formed in the semiconductor chip and configured to control a conductive/non-conductive state of the current path of the switching element

Semiconductor integrated circuit and method for testing same

Abstract: PROBLEM TO BE SOLVED: To provide semiconductor integrated circuits which can be driven by respectively different power supply voltages in accordance with manufacturing dispersion, and provide a test method for guaranteeing the operation. SOLUTION: In addition to a function block to be driven by receiving supply of power supply voltage, the semiconductor integrated circuit 10 comprises a process monitor circuit 11 for grasping a delay characteristic corresponding to a manufacturing process condition; a storage circuit 12 for storing data concerned with a process dispersion state acquired from the process monitor circuit 11; and a power supply voltage control circuit 13 for adaptively controlling the power supply voltage in accordance with the process dispersion state acquired from the process monitor circuit 11 and stored in the storage circuit 12. COPYRIGHT: (C)2006,JPO&NCIPI

Low power sleep mode operation technique for dynamic random access memory (DRAM) devices and integrated circuit devices incorporating embedded DRAM

Abstract: A low power Sleep Mode operation technique for dynamic random access (DRAM) devices and integrated circuit devices incorporating embedded DRAM. By counting clock (CLK) cycles in accordance with the technique disclosed, refresh time (tREF) does not vary with all possible process corners, voltages and temperatures (PVT) since the clock signal exhibits a steady frequency over PVT applied to the DRAM and an internal timer placed on chip will vary directly with these parameters. After entering Sleep Mode, the main internal clock signal is inhibited from propagating around the device chip and, at this time, much of the associated circuitry can be power-gated to conserve power, typically with signals that have a boosted level to provide a negative gate-to-source voltage (VGS) on the power-gating transistors.

1.0 Gbps LVDS transceiver design for LCD panels

Abstract: LVDS has become a popular choice for high-speed serial links in large-sized display units. This work presents the design and implementation of I/O interface circuits for Gbps operation which is fully complied with the IEEE STD. 1596.3 (LVDS). A step-down voltage regulator is employed to reject the noise coupled in the system power supply. A CMFB (common mode feedback) circuitry is utilized in the transmitter to stabilize the common mode voltage in a predefined range. By contrast, a regenerative circuit which provides a positive feedback loop gain between the preamplifier and the output buffer in the receiver. A typical 0.25 /spl mu/m 1P5M CMOS technology is used to realize the proposed LVDS transceiver. The post-layout simulation reveals that the data rate is 1.0 Gbps at all process corners.

Providing optimal supply voltage to integrated circuits

Abstract: A characteristic is measured on multiple portions of an integrated circuit, and the supply voltage adjusted based on the measurements. In an embodiment, the characteristic corresponds to propagation delay which indicates whether the integrated circuit is implemented with a strong, weak or nominal process corner. In general, the supply voltage can be increased in the case of a weak process corner and decreased in the case of a strong process corner.

Highly reliable, cost effective and thermally enhanced AuSn die-attach technology

Abstract: The present invention relates to a circuit, an integrated circuit package and methods for attaching integrated circuit dies or discrete power components to flanges of integrated circuit packages, wherein each of said integrated circuit dies is sawed from a wafer. The invention comprises reducing the thickness of said wafer by mechanical grinding, applying an isotropic wet chemical etching to said wafer to eliminate crystal defects, evaporating adhesion and diffusion barrier metals on the backside of said wafer, evaporating Au and Sn on the backside of the wafer, wherein the weight proportion of Au is equal to or larger than 85%, sawing the wafer into said circuit dies, and soldering each of said circuit dies to a respective flange of an integrated circuit package.

A statistical model based ASIC skew selection method

Abstract: Cross wafer speed variations in the 0.13 /spl mu/m process and beyond are significant enough to be considered in ASIC skew selection. Traditional Idsat and Vt measurements on a few sites of the wafer to gauge wafer speed simply does not work. Multiple skew lot runs to get proper skew wafers is financially prohibitive and part skew uncertainty makes it impossible to qualify product with a reasonable number of skew parts. Typical design practice for high-speed ASICs is to add a PVT monitor on the die. For area critical applications, scribe PVT monitors can be used. The PVT circuitry can be as simple as an inverter ring oscillator chain. We present a methodology based on on-chip or on-scribe ring oscillator data to bin the ASIC skew parts. Statistical modeling, PVT monitor sensitivity and actual experiment data are discussed. Based on the proposed methodology, proper skew parts can be selected for product testing so that products are validated cross all process corners.

A low distortion and fast settling automatic gain control amplifier in CMOS technology

Abstract: This paper presents an automatic gain control (AGC) circuit with the improvement of the harmonic distortion and tracking time in CMOS technology. A configuration, which is comprised of V-V converters and a corner tracker, is proposed to extend the linear-in-dB range of the variable gain amplifier (VGA) and to increase the tolerance of the circuit to process corner variation. A new comparator technique is introduced to speed up the tracking time of the AGC circuit and to reduce the acquisition time of the system. The AGC consumes 8 mA current and has a 100 MHz 3-dB bandwidth in 0.35 /spl mu/m CMOS technology, which is suitable to the use in IF amplifier in modern wireless communication systems.

Built-In Current Sensor for IDDQ Testing

Abstract: This paper presents the implementation of a built-in current sensor for DDQ testing. In contrast to conventional built-in current monitors, this implementation has three distinctive features: 1) built-in self-calibration to the process corner in which the circuit under test was fabricated; 2) digital encoding of the quiescent current of the circuit under test for robustness purposes; and 3) enabling versatile testing strategy through the implementation of two advanced DDQ testing algorithms. The monitor has been manufactured in a 0.18m CMOS technology and it is based on the principle of disconnecting the device under test from the power supply during the testing phase. The monitor has a resolution of 1 A for a background current less than 100 A or 1% of background currents over 100 A to a total of 1-mA full scale. The sensor operates at a maximum clock speed of 250 MHz. The quiescent current is indirectly determined by counting a number of clock pulses which occur during the time the voltage at the disconnected node drops below a reference voltage value. Basically, at the end of the count period, the counted value is inversely proportional to the quiescent current of the device under test. Then, a DDQ unit processes the counted number and the outcome is compared with a reference number to determine whether a defect exists in the device under test. Accuracy is improved by adjusting the value of the reference number and the frequency of the clock signal depending upon the particular process corner of the circuit under test. The monitor has been verified in a test chip consisting of one “DSP-like” circuit of about 250,000 transistors. Experimental results prove the usefulness of our approach as a quick and effective means for detecting defects.

Semiconductor device, system device using it, and manufacturing method of a semiconductor device

Abstract: To reduce the size and the power consumption of a semiconductor device. A first circuit having a prescribed circuit function is provided. A second circuit which can be connected to the first circuit externally gives the first circuit a non-always-used particular function so that the first circuit can perform the particular function.

A tunable g/sub m/-C filter with low variation across process, voltage and temperature

Abstract: A tunable g/sub m/-C filter with cutoff frequency insensitive to Process, Voltage and Temperature is proposed. An external clock frequency is used to generate a current using a switched capacitor circuit. The proposed filter is ideally suited for applications where a tight control on cutoff frequency is desired across different operating conditions of the chip. The circuit was designed in 3.3 V BiCMOS technology and simulations were carried out using SPICE. The simulation results show that the total variation in the cutoff frequency is 1% as compared to the 27% variation in conventional g/sub m/-C filter over the temperature range of -40 to 120 degC. The variation across process corners is 2.4% and is almost independent of the capacitor variation due to process and temperature.

Clock recovery and data recovery design for LVDS transceiver used in LCD panels

Abstract: This paper presents the design and implementation of a CDR (clock and data recovery) design for LVDS transceiver operations. Instead of using an oversampling scheme, which requires a high-speed clock generator, we adopt an interpolation scheme, which relaxes the demand of a high-speed PLL with very high precision. A dual-tracking design is proposed to precisely align both edges of a data eye. Hence, the center of a data eye can be optimally sampled. A typical 0.25 /spl mu/m 1P5M CMOS technology is used to realize the proposed dual-tracking CDR for 7/spl times/100 (bit-MHz) LVDS signaling. The post-layout simulation reveals that the worst-case jitter of the sampling clocks is less than 450 ps (peak-to-peak) and 250 ps (rms) at all process corners.

Clock recovery and data recovery design for LVDS transceiver used in LCD panels

Abstract: This work presents the design and implementation of a CDR (clock and data recovery) design for LVDS transceiver operations Instead of using an oversampling scheme which requires a high-speed clock generator, we adopt an interpolation scheme which relaxes the demand of a high-speed PLL with a very high precision A dual-tracking design is proposed to precisely align both edges of a data eye Hence, the center of a data eye can be optimally sampled A typical 025 /spl mu/m 1P5M CMOS technology is used to realize the proposed dual-tracking CDR for 7/spl times/100 (bit-MHz) LVDS signaling The post-layout simulation reveals that the worst-case jitter of the sampling clocks is less than 450 ps (peak-to-peak) and 250 ps (rms) at all process corners

Technology for three dimensional integrated system-on-a-chip

Abstract: We have proposed a wafer stacking technology to integrate various kinds of devices into 3D SoC In 3D SoC each circuit layer is stacked and electrically connected vertically using a huge number of vertical interconnection Hence, we can dramatically increase the wiring connectivity, reduce the number of long wiring and integrate various kinds of devices with different fabrication process sequences into one chip In this paper, we describe a 3D microprocessor test chip consisting of three circuit layers and demonstrate the basic operation of the 3D microprocessor

Wafer having thermal circuit and power supplier therefor

Abstract: Provided are a wafer having a thermal circuit and power supplier therefor, which enable the wafer to heat or cool itself without using any additional heating or cooling system. The wafer includes the thermal circuit that is installed on one side of the wafer to be capable of self-heating or self-cooling the wafer in order to perform a heating process or cooling process on a semiconductor device formed on the surface of the wafer and exchanges heat with the semiconductor device. Thus, a temperature of a semiconductor device can be precisely controlled, and heating and cooling energies are greatly reduced through a direct heat exchange method, thus attaining high efficiency. Since the thermal circuit is directly installed in the wafer, it is structurally simple and the costs of production and installation can be notably reduced. Also, the present invention is very advantageous for optimization, miniaturization, simplification, and environmentally friendly production of a wafer heating/cooling system. Furthermore, a temperature measuring circuit is installed on a reverse surface of the wafer so that the amount of energy that acts on an actual semiconductor device or actual temperature can be accurately measured in real time.

Wafer having alternating design structure and method for manufacturing semiconductor package using the same

Abstract: The present invention relates to a wafer having an alternating design structure and a method for manufacturing a semiconductor package using the wafer. The present invention is conceived to solve all the aforementioned problems associated with the related art wafer having the lattice design arrangement and method for manufacturing a semiconductor package using the wafer. According to the present invention, the number of dies per wafer can be maximized (6 to 8 % of dies per wafer can be further produced) as compared to the conventional lattice design arrangement to allow the manufacturing costs of dies to be lowered by designing the wafer to have an alternating arrangement design structure. Further, the time taken to inspect dies can be remarkably reduced through the improvement in efficiency of a die tester by allowing the die to be inspected using a carrier when manufacturing the semiconductor package. In addition, the manufacturing process can be simplified by omitting an inking process for indexing reject dies, which has been essentially performed in the related art semiconductor package manufacturing process. Furthermore, the productivity improvement and in-line automation can be achieved by mounting a carrier with dies for the handling of the dies by the carrier, thereby contributing to reduction in price of the semiconductor manufacturing equipment.

Configuring a performance state of an integrated circuit die on wafer

Abstract: Techniques for configuring a performance state of an integrated circuit die that do not consume input/output pin connections to the integrated circuit die. An integrated circuit die according to the present teachings includes a set of configuration lines. Each configuration line determines a performance characteristic of the integrated circuit die. The integrated circuit die is configured for a performance state while on a wafer by cutting one or more of the configuration lines.

A worst-case circuit delay verification technique considering power grid voltage variations

Abstract: In the verification of VLSI circuit design, static timing analysis (STA) techniques allow a designer to calculate the timing of a circuit at different process corners, which only consider cases where all the supplies are low or high. This analysis may not be the true maximum delay of a circuit due to the neglect of mismatch between drivers and load. We propose a new methodology for timing analysis where we identify all the possible critical paths of a circuit using new timing models while integrating the aforementioned mismatch for the logic gates. Given then these critical paths we tie the supplies of the gates to physical power grids and re-analyze for the worst-case time delay. This re-analysis is posed as a sequence of optimization problems where the complete operation of the entire circuit is abstracted in terms of current constraints. We present our technique and report on the implementation results using benchmark circuits tied to a number of test-case power grids.

A 260ps Quasi-static ALU in 90nm CMOS

Abstract: A 32-bit ALU has been implemented in the baseline Philips-Motorola-ST 0.10um triple-VT CMOS technology. The ALU core has been designed with a combined dynamic/static design approach aiming at high-speed operation and standard cells based design. It runs at frequencies ranging from 3.8 GHz to 5.4 GHz (with nominal supply at room temperature) depending on the actual fabrication process corner.