Showing papers on "Process corners published in 2005"

Systems, methods, and apparatus to perform statistical static timing analysis

Abstract: A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners using a static timing analysis module, and estimating performance of the circuit at a predetermined confidence level based on results of the statistical analysis during an automated design flow of the circuit without using libraries at the predetermined confidence level.

Statistical gate sizing for timing yield optimization

Abstract: Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely over-constrains the system and results in solutions with excessive penalties. Statistical timing analysis and optimization have consequently emerged as a refinement of the traditional static timing approach for circuit design optimization. In this paper, we propose a statistical gate sizing methodology for timing yield improvement. We build statistical models for gate delays from library characterizations at multiple process corners and operating conditions. Statistical timing analysis is performed, which drives gate sizing for timing yield optimization. Experimental results are reported for the ISCAS and MCNC benchmarks. In addition, we provide insight into statistical properties of gate delays for a given technology library which intuitively explains when and why statistical optimization improves over static timing optimization.

OPERA: optimization with ellipsoidal uncertainty for robust analog IC design

Abstract: As the design-manufacturing interface becomes increasingly complicated with IC technology scaling, the corresponding process variability poses great challenges for nanoscale analog/RF design. Design optimization based on the enumeration of process corners has been widely used , but can suffer from inefficiency and overdesign. In this paper we propose to formulate the analog and RF design with variability problem as a special type of robust optimization problem, namely robust geometric programming. The statistical variations in both the process parameters and design variables are captured by a pre-specified confidence ellipsoid. Using such optimization with ellipsoidal uncertainy approach, robust design can be obtained with guaranteed yield bound and lower design cost, and most importantly, the problem size grows linearly with number of uncertain parameters. Numerical examples demonstrate the efficiency and reveal the trade-off between the design cost versus the yield requirement. We will also demonstrate significant improvement in the design cost using this approach compared with corner-enumeration optimization.

0.18-/spl mu/m CMOS equalization techniques for 10-Gb/s fiber optical communication links

Abstract: Limitations in data transmission caused by modal dispersion in fiber-optic links can be significantly improved using equalization techniques. In this paper, two different equalizer implementation approaches are proposed to extend the transmission capacities of existing fiber-optic links. The building blocks of the equalizer including a multiplier cell, a delay line, and an output buffer stage are fully integrated on a 0.18-/spl mu/m CMOS process. For the continuous-time tap-delay implementation, a passive LC delay line and an active inductance peaking delay line are compared for performance against process variation, as well as power consumption. In addition, a delay-locked loop is proposed to counter delay variations caused by changes in the process corner. A 10-Gb/s nonreturn-to-zero signal is received after transmission through a 500-m multimode-fiber channel, and the signal impairment due to the differential modal delay is successfully compensated using both feed-forward equalizers.

DVS for On-Chip Bus Designs Based on Timing Error Correction

Abstract: On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching pattern. This can result in significant performance slack at more typical operating conditions. In this paper, we propose a dynamic voltage scaling (DVS) technique for buses, based on a double sampling latch which can detect and correct for delay errors without the need for retransmission. The proposed approach recovers the available slack at non-worst-case operating points through more aggressive voltage scaling and tracks changing conditions by monitoring the error recovery rate. Voltage margins needed in traditional designs to accommodate worst-case performance conditions are therefore eliminated, resulting in a significant improvement in energy efficiency. The approach was implemented for a 6mm memory read bus operating at 1.5GHz (0.13 µm technology node) and was simulated for a number of benchmark programs. Even at the worst-case process and environment conditions, energy gains of up to 17% are achieved, with error recovery rates under 2.3%. At more typical process and environment conditions, energy gains range from 35% to 45%, with a performance degradation under 2%. An analysis of optimum interconnect architectures for maximizing energy gains with this approach shows that the proposed approach performs well with technology scaling.

Parameter variation on chip-level

Abstract: Integrated MOSFET circuits fabricated in actual technologies are packed on several square millimetres of chip area. Circuit building blocks distributed over a chip have to achieve the same specifications. The circuit features depend on device parameters which vary not only on a global scale (i.e., wafer scale) or on a local scale (i.e., close-packed device pairs) but also on a chip-level scale. A concept for characterization of intra-die-statistics is discussed which closes the gap between process control monitoring and matching characterization.

Digitally controlled oscillator for reduced power over process variations

Abstract: This disclosure relates to a cell-placeable variable-frequency digitally controlled oscillator (DCO) that consumes approximately the same current in a fast process corner as in the case of a slow process corner. By modulating the effective channel length of transistors in inverters, a fast process DCO may be slowed down to a desired frequency at nearly the same current consumption as that of a slow process DCO.

Post-layout parasitic verification methodology for mixed-signal designs using fast-SPICE simulators

Abstract: Current sub-100 nanometer processes employ complex multilayer metallization structures with advanced dielectric materials. Closely-spaced thin, tall metal interconnects with low voltage and fast-clocking edges lead to circuit performances dominated by parasitic delays. Various issues such as noise and delay associated with cross-talk due to coupling capacitances; IR drop effects in the low power supply operating regimes; high current density causing electromigration in narrow interconnect structures; and DC path leakage currents are becoming very common effects in recent mixed-signal designs. Full-chip, post-layout simulation with extracted parasitic components is required in the design flow to accurately analyze each of these effects. Due to the presence of a large amount of parasitics, it is important to extract appropriate parasitics for the relevant process corners and perform the analysis. Fast-spice simulator-based flows are becoming prevalent due to their capacity and efficiency in handling large amounts of data. In this paper, we discuss various options available for designers using fast-spice simulators (e.g. UltraSim, NanoSim, and HSIM) for post-layout simulations, and how these options affect the end results. We have simulated the design with 2.5 million RC elements in 13 hours using a fast-spice simulator. A few examples of post-layout simulations carried out on designs will be discussed.

Semiconductor integrated circuit and method of testing same

Abstract: A semiconductor integrated circuit able to operate by different power supply voltages resulting from fluctuations in production, provided with a process monitor circuit for obtaining a grasp of a delay characteristic corresponding to the conditions of a production process, a memory circuit for storing data concerning an extent of process variation acquired by the process monitor circuit, and a power supply voltage control circuit for adaptively controlling the power supply voltage in accordance with the extent of process variation acquired by the process monitor circuit and stored in the memory circuit, and a test method for guaranteeing the operation of the semiconductor integrated circuit.

Semiconductor die with process variation compensated operating voltage

Abstract: A semiconductor die includes at least one process monitoring circuit for evaluating at least one process parameter of the semiconductor die. The at least one process monitoring circuit can include a first group of process monitoring circuits for monitoring NFET speed and a second group of process monitoring circuits for monitoring PFET speed. The process monitoring circuits can be distributed at the corners of the semiconductor die. The semiconductor die further includes a voltage control circuit configured to store optimum voltage information corresponding to the at least one process parameter. The voltage control circuit is further configured to selectively provide the optimum voltage information to a system power supply. The voltage control circuit includes a calculated optimum voltage register that stores the optimum voltage information corresponding to the at least one process parameter.

Method of processing semiconductor wafer

Abstract: A method of processing a semiconductor wafer is provided. The semiconductor wafer is processed with a first process. After collecting the measured data that reflects the deviation of each part within the semiconductor wafer, the semiconductor wafer is processed with a second process according to the measured data to compensate the deviation from the first process and to correct any deviation in the semiconductor wafer.

Semiconductor circuit board and semiconductor circuit

Abstract: The present invention is intended to efficiently implement noise countermeasures for a semiconductor circuit board and for a semiconductor circuit. The present invention is constituted by a control substrate, and a semiconductor circuit connected to the control substrate. The semiconductor circuit includes a substrate, an integrated circuit group, and a noise countermeasure, and is separated from the control substrate. The integrated circuit group includes an integrated circuit as a noise source. The substrate has a stacked multilayer structure, and shifts the frequency of a noise generated by the integrated circuit group to the high frequency side. The noise countermeasure is connected between the integrated circuit group and the control substrate. The noise countermeasure is a filter for attenuating the high frequency of a noise.

A process variation tolerant technique for sub-70nm latches and flip-flops

Abstract: This paper describes a sub-70nm circuit technique that compensates the impact of the increasingly large process variations on latches and flip-flops. In contrast to the traditional design for worst-case process corners, we utilize a variable keeper circuit that preserves the robustness of storage nodes across the process corners, without degrading the overall chip performance. Power and delay improvements of 7% and 12% respectively have been observed for wide static MUX-latch circuits in a 65nm CMOS technology. Moreover, the proposed technique enables functional flip-flops with weak uninterrupted keepers leading to over 9% clock power reduction.

Inspection method and inspection apparatus for semiconductor integrated circuit

Abstract: In a semiconductor integrated circuit inspection method of inspecting a semiconductor integrated circuit comprising plural transistors according to which a test pattern generated for the semiconductor integrated circuit is input to an input terminal of the semiconductor integrated circuit, the time during which a voltage applied upon each of the transistors remains equal to or higher than a predetermined voltage is measured in response to inputting of the test pattern at the input terminal, and the ratio of thus measured time to the inspection time for the semiconductor integrated circuit is calculated.

Distortion reducing semiconductor switch

Abstract: A semiconductor switch includes a first semiconductor circuit having a nonlinear characteristic, and a second semiconductor circuit having a nonlinear characteristic. Each of the first semiconductor circuit and the second semiconductor circuit is configured to at least one of allow and interrupt transmission of a signal. The first semiconductor circuit reduces the nonlinear characteristic of the second semiconductor circuit and the second semiconductor circuit reduces the nonlinear characteristic of the first semiconductor circuit.

A low-voltage high-PSRR CMOS PTAT & constant-g/sub m/ reference circuit

Abstract: The design of a good PTAT current reference plays a very important role in the design of bandgap reference circuits Using a high-swing low-voltage current mirror, a low-voltage high-PSRR current reference circuit is presented Simulation results of the circuit confirm its proper operation with a low supply voltage of 13V within a wide thermal range of -50degC to +130degC It shows a constant gm value with 05% variation in all process corners

Semiconductor integrated circuit and fabrication process thereof

Abstract: A semiconductor integrated circuit that includes thereon a flash memory and a plurality of MOS transistors using different power supply voltages is formed by a process in which a thermal oxidation process is applied to one of the device regions while covering the other device regions by an oxidation-resistant film.

Design method for semiconductor integrated circuit device

Abstract: A design method for a semiconductor integrated circuit device. For a path having a signal arrival time exceeding a desired value, among paths in the semiconductor integrated circuit device, a path separation is performed so that the number of other components to be connected to the output of a component belonging to the path decreases. By this, it is possible to provide a design method that can implement higher performance and higher speed of the semiconductor integrated circuit device, and to provide a design method that can be integrated into the automatic design flow using conventional EDA tools and can implement higher performance and higher speed than conventional technology.

Low power quadrature generation using injection-locked ring oscillator divider

Abstract: A low power high frequency quadrature generator is described. The circuit output frequency is locked at one-fourth of the input injection frequency and provides quadrature output signals. The circuit can be used as the first stage of a phase switching prescaler or as a divider with a divide value of two in the quadrature mixer of a transceiver. For -2 dBm injection level, circuit works properly in all process corners and a temperature range of -20degC to +100degC with maximum 3 GHz operation frequency while its locking range is over than 1 GHz. Power consumption at maximum frequency is 528 muW at the supply voltage of 1.5 V.

Design of a 12-bit 80-MS/s CMOS digital-to-analog converter for PLC-VDSL applications

Abstract: This paper describes the design of a 12-bit 80MS/s Digital-to-Analog converter implemented in 0.13mm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog converters in MATLAB. The embedded simulator uses SIMULINK C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time and makes the proposed tool an advantageous alternative for fast exploration of requirements and as a design validation tool. The converter is segmented in a unary current-cell matrix for 8 MSB's and a binary-weighted array for 4 LSB's. Current sources of the converter are laid out separately from current-cell switching matrix core block and distribute in double centroid to reduce random errors and transient noise coupling. The linearity errors caused by remaining gradient errors are reduced by a modified Q2 Random-Walk switching sequence. Simulation results show that the Spurious-Free Dynamic-Range is better than 58.5dB up to 80MS/s. The estimated Signal-to-Noise Distortion Ratio yield is 99.7% and it is supposed to be better than 58dB from DC to Nyquist frequency. Multi-Tone Power Ratio is higher 59dB for several DMT test signals. The converter dissipates less than 129mW from a 3.3V supply and occupies less than 1.7mm2 die area. The results have been checked with all process corners from -40° to 85° and power supply from 3V to 3.6V.© (2005) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Design of a 12-bit 80MS/s pipeline analog-to-digital converter for PLC-VDSL applications

Abstract: This paper describes the design of a 12-bit 80MS/s pipeline Analog-to-Digital converter implemented in 0.13mm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation, synthesis and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog Converters in MATLAB. The embedded simulator uses SIMULINK C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time and makes the proposed tool an advantageous alternative for fast exploration of requirements and as a design validation tool. The converter is based on a 10-stage pipeline preceded by a sample/hold with bootstrapping technique. Each stage gives 1.5 effective bits, except for the first one which provides 2.5 effective bits to improve linearity. The Analog-to-Digital architecture uses redundant bits for digital correction, it is planned to be implemented without using calibration and employs a subranging pipeline look-ahead technique to increase speed. Substrate biased MOSFETs in the depletion region are used as capacitors, linearized by a series compensation. Simulation results show that the Multi-Tone Power Ratio is higher than 56dB for several DMT test signals and the estimated Signal-to-Noise Ratio yield is supposed to be better than 62 dB from DC to Nyquist frequency. The converter dissipates less than 150mW from a 3.3V supply and occupies less than 4 mm2 die area. The results have been checked with all process corners from -40° to 85° and power supply from 3V to 3.6V.© (2005) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.