Showing papers on "Process corners published in 2011"

Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 $\mu$ m HV-CMOS Technology

Abstract: We present novel circuits for high-voltage digital level shifting with zero static power consumption. The conventional topology is analysed, showing the strong dependence of speed and dynamic power on circuit area. Novel techniques are shown to circumvent this and speed up the operation of the conventional level-shifter architecture by a factor of 5-10 typically and 30-190 in the worst case. In addition, these circuits use 50% less silicon area and exhibit a factor of 20-80 lower dynamic power consumption typically. Design guidelines and equations are given to make the design robust over process corners, ensuring good production yield. The circuits were fabricated in a 0.35 high-voltage CMOS process and verified. Due to power and IO speed limitation on the test chip, a special ring oscillator and divider structure was used to measure inherent circuit speed.

Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique

Abstract: The increasing variability in device leakage has made the design of keepers for wide OR structures a challenging task. The conventional feedback keepers (CONV) can no longer improve the performance of wide dynamic gates for the future technologies. In this paper, we propose an adaptive keeper technique called rate sensing keeper (RSK) that enables faster switching and tracks the variation across different process corners. It can switch upto 1.9t faster (for 20 legs) than CONV and can scale upto 32 legs as against 20 legs for CONV in a 130-nm 1.2-V process. The delay tracking is within 8% across the different process corners. We demonstrate the circuit operation of RSK using a 32 t 8 register file implemented in an industrial 130-nm 1.2-V CMOS process. The performance of individual dynamic logic gates are also evaluated on chip for various keeper techniques. We show that the RSK technique gives superior performance compared to the other alternatives such as Conditional Keeper (CKP) and current mirror-based keeper (LCR).

Static Noise Margin of 6T SRAM Cell in 90-nm CMOS

Abstract: This paper examines the factors that affect the Static Noise Margin (SNM) of a 6T Static Random Access Memory (SRAM) cell designed in 90-nm CMOS. In this paper, the SRAM cell is simulated and noise margins are obtained while varying several parameters that affect SRAM operations. These parameters are temperature, threshold voltage, supply voltage, cell ratio, pull-up ratio, and process corner variations. The simulation results were found to be in agreement with the model derived by Seevinck et al. [1] which is based on the square law device model.

Multi-objective optimization techniques for VLSI circuits

Abstract: The EDA design flows must be retooled to cope with the rapid increase in the number of operational modes and process corners for a VLSI circuit, which in turn results in different and sometimes conflicting design goals and requirements. Single-objective solutions to various design optimization problems, ranging from sizing and fanout optimization to technology mapping and cell placement, must hence be augmented to deal with this changing landscape. This paper starts off by presenting a variety of methods for providing analytical models for power and delay to be used in the optimization algorithms. The modeling includes non-convex and convex functional forms. Next, a class of robust and scalable methods for solving multi-objective optimization problems (MOP) in a digital circuit is presented. We present the results of a multi-objective (i.e., power dissipation and delay) gate (transistor) sizing optimization algorithm to demonstrate the effectiveness of our method. We set up the problem as a simultaneous, multi-objective optimization problem and solve it by using the Weighted Sum and Compromise Programming methods. After comparing these two methods, we present the Satisficing Trade-off Method (STOM) to find the most desirable operating point of a circuit.

Ring based impedance control of an output driver

Abstract: In one embodiment, there is a method that can include utilizing a ring oscillator module to determine a process corner of an integrated circuit as fabricated that includes the ring oscillator module. The impedance of an output driver of the integrated circuit can be altered based on the process corner of the integrated circuit as fabricated.

A 40-nm 0.5-V 20.1-µW/MHz 8T SRAM with low-energy disturb mitigation scheme

Abstract: This paper presents a novel disturb mitigation scheme which achieves low-power and low-voltage operation for a deep sub-micron SRAM macro. The classic write-back scheme overcame a half-select problem and improved a yield; however, the conventional scheme consumed more power due to charging and discharging all write bitlines (WBLs) in a sub block. Our proposed scheme consists of a floating bitline technique and a low-swing bitline driver (LSBD). This scheme decreases active leakage and active power by 33% and 32% at the FF corner, respectively. In other process corners, more active power reduction can be expected. We fabricated a 512-Kb 8T SRAM test chip that operates at a single 0.5-V supply voltage. The proposed scheme achieves 8.8-µW/MHz active energy in a write cycle and 72.8-µW leakage power, which are 35% and 26% better than the conventional write-back scheme. The total energy is 20.1 µW/MHz at 0.5 V in a 50%-read/50%-write operation.

Offset-corrected 5GHz CMOS dynamic comparator using bulk voltage trimming: Design and analysis

Abstract: This paper presents an improved two-stage dynamic comparator using a bulk voltage trimming technique for offset calibration. The comparator requires only a one-phase clock while exerting no extra load on the first stage, leading to higher operating speed. The calibration does not require any extra power supply and does not consume any quiescent current, while increasing the offset calibrating range by a factor of 2 over previous techniques. Detailed analysis of the method of calibrating both stages of the dynamic comparator is provided. Simulation results in a 65nm digital CMOS process show that the comparator is capable of working at a speed of 5GHz with 90uW of power consumption from a 1V power supply, achieving an input-referred offset calibrating range of ±35mV at ∼±2.3mV/step at the typical-typical process corner.

A fast approach for static timing analysis covering all PVT corners

Abstract: The increasing sensitivity of circuit performance to process, temperature, and supply voltage (PVT) variations has led to an increase in the number of process corners that are required to verify circuit timing. Typically, designers attempt to reduce this computational load by choosing, based on experience, a subset of the available corners and running static timing analysis (STA) at only these corners. Although running a few corners, which are chosen beforehand, can lead to acceptable results in some cases, this is not always the case. Our results show that in the case of setup timing analysis, one can indeed bound circuit slacks across all corners by running a small number of corners. On the other hand, we show that this is not possible in the case of hold analysis. Instead, we present an alternative method for performing fast and accurate hold timing analysis which covers all corners. In this method a full timing run is performed for a small number of corners, and partial timing runs, which cover only the clock network, are performed for others. We then combine the results of the full and partial runs to find the worst-case hold slacks over all corners. Our results show that this method is accurate and can achieve much improved runtimes.

Linear vt-based temperature sensors with low process sensitivity and improved power supply headroom

Abstract: A new on-die temperature sensor that operates at low supply voltages and exhibits low process sensitivity and good linearity over a wide temperature range is introduced. When compared to conventional structures which have limited supply voltage headroom at the slow-n process corner, the new structures have sufficient headroom to practically operate well over all process corners. When implemented in a TSMC 0.18um process with a nominal supply voltage of 1.8V, simulation results show the maximum temperature linearity error is reduced from 1.5°C to less than 0.3°C at the NMOS slow process corner and with negative 10% Vdd variation.

Tri-Mode Independent-Gate FinFETs for Dynamic Voltage/Frequency Scalable 6T SRAMs

Abstract: In this paper, we present tri-mode independent-gate (IG) FinFETs for dynamic voltage/frequency scalable 6T SRAMs. The proposed design exploits the fact that the spacer patterning technology, used for FinFET fabrication, offers the same device footprint for two- and one-fin transistors. The access transistor is designed for operation in three on-state modes achieving simultaneous increase in the read stability and write-ability and enabling appropriate tradeoffs between read stability and access time depending on the frequency requirements. The proposed design achieves 40%-48% higher weak-write test voltage and 2%-34% lower cell write time across a range of voltages compared with a conventional FinFET-based 6T SRAM under iso-leakage. During the read operation at high workload conditions (VDD = 0.7 V), 8% improvement in read static noise margin (SNM) is achieved with only 7% access time penalty. During the read operation at low workload conditions, 54%-75% improvement in the read SNM enables low voltage operation under process variations. The proposed IG FinFET SRAM achieves 125-136 mV lower VMIN across different global process corners at the cost of 15-mV higher retention VMIN. Iso-leakage comparison of the proposed technique with the previously proposed IG FinFET 6T SRAM is also performed. An increase in the cell area by 35% is observed compared to the minimum-sized conventional FinFET SRAM. However, there is no cell area penalty compared to the previously proposed IG FinFET SRAM.

Analysis of 8T SRAM Cell at Various Process Corners at 65 nm Process Technology

Abstract: In Present scenario battery-powered hand-held multimedia systems become popular. The power consumption in these devices is a major concern these days for its long operational life. Although various techniques to reduce the power dissipation has been developed. The most adopted method is to lower the supply voltage. But lowering the Vdd reduces the gate current much more rapidly than the sub-threshold current and degrades the SNM. This degraded SNM further limits the voltage scaling. To improve the stability of the SRAM cell topology of the conventional 6T Static Random Access Memory (SRAM) cell has been changed and revised to 8T and 10T cell, the topologies. This work has analyzed the SRAM’s Static Noise Margin (SNM) at 8T for various process corners at 65nm technology. It evaluates the SNM along with the write margins of the cell along with the cell size of 8T SRAM bit-cell operating in sub-threshold voltage at various process corners. It is observed that an 8T cell has 13 % better write margin than conventional 6T SRAM cell. This paper analyses the dependence of SNM of SRAM memory cell on supply voltage, temperature, transistor sizing in 65nm technology at various process corners (TT, SS, FF, FS, and SF).

Modeling method of MOS (Metal Oxide Semiconductor) transistor process corner SPICE (Simulation Program for Integrated Circuits Emphasis) model

Abstract: The invention provides a modeling method of an MOS (Metal Oxide Semiconductor) transistor process corner SPICE (Simulation Program for Integrated Circuits Emphasis) model, which comprises the following steps: according to collected statistic information of characteristics of a simulated MOS transistor process line device, selecting 14 parameters of a PSP (Personal Software Process) model, and finally obtaining an MOS transistor process corner PSP model card. The MOS transistor process corner PSP model based on the PSP model is a new model used for an MOS transistor SPICE simulation model. By using the modeling method of the new MOS transistor process corner SPICE model, the MOS transistor process corner SPICE model having favorable fitness of simulation and test result can be quickly obtained, and the yield of an integrated circuit composed of the process line MOS transistor device is greatly improved.

Reducing power dissipation using process corner information

Abstract: In one embodiment, the present invention includes a method for determining process corner information of an integrated circuit (IC) and controlling at least one analog current for at least one analog circuit of the IC based on the process corner information. More specifically, if the process corner information is indicative of a fast corner IC, the analog current may be scaled down. At the same time that the analog current is scaled down, a current consumption level of digital circuitry of the IC may increase. In this way, overall power consumption of the IC may be reduced to the extent that the analog current(s) are scaled.

Design of a CMOS Bandgap Reference with Low Temperature Coefficient and High Power Supply Rejection Performance

Abstract: A high precision temperature compensated CMOS bandgap reference is presented. The proposed circuit employs current-mode architecture that improves the temperature stability of the output reference voltage as well as the power supply rejection when compared to the conventional voltage-mode bandgap referenc. Using only first order compensation the new architecture can generate an output reference voltage of 550mV with a peak-to-peak variation of 400μV over a wide temperature range from -25 o C to +100 o C which corresponds to a temperature coefficient of 5.8ppm/oC. The output reference voltage exhibits a variation of 2.4mV for supply voltage ranging from 1.6V to 2.0V at typical process corner. A differential cascaded three-stage operational amplifier is included in the bandgap circuit to improve the power supply rejection of the BGR. Simulation result shows that the power supply rejection ratio of the proposed circuit is 79dB from DC up to 1kHz of frequency. The proposed bandgap reference is implemented using UMC 0.18μm CMOS process and it occupies an active layout area of 0.14mm 2 .

Process variation compensated voltage controlled ring oscillator with Subtraction-based Voltage Controlled Current Source

Abstract: In this work, we present a process variation compensated voltage-controlled ring oscillator (VCO) with the new Subtraction-based Voltage-Controlled Current Source (S-VCCS). The Subtraction-based Voltage-Controlled Current Source supplies the oscillator with a relatively stable current across process corners. A current starved ring oscillator structure with the proposed subtraction-based current source has been designed using the IBM 0.13μm CMOS technology. Simulation results have shown that the proposed design using Subtraction-based Voltage Controlled Current Source (S-VCCS) can achieve approximately 50% reduction of the VCO's process-induced frequency variation when compared to standard approach.

Characterization of 9T SRAM Cell at Various Process Corners at Deep Sub-micron Technology for Multimedia Applications

Abstract: In the past decades CMOS IC technologies have been constantly scaled down and at present they aggressively entered in the nanometer regime. Amongst the wide-ranging variety of circuit applications, integrated memories especially the SRAM cell layout has been significantly reduced. As it is very well know the reduction of size of CMOS involves an increase in physical parameters variation, this is a factor which has a direct impact on SRAM cell stability. Polysilicon and diffusion critical dimensions (CD) together with implant variations are the main causes of mismatch in SRAM cells. SRAM memory cells have always been designed to occupy the minimum amount of silicon area consistent with the performance and reliability required. Today's system on Chip (SoC) trends result in a major percentage of the total die area being dedicated to memory blocks, consequently making SRAM parameter variations dominate the overall circuit parameter characteristics, including leakage, process variation effects, etc. The reliability is usually measured by static noise margin, SNM (1), and write trip point simulations and measurements. In this paper we have analyzed the stability of the 9T SRAM cell at SS, FF, TT, FS, SF corners. The simulations have been done at 45nm technology.

Circuit used for indicating process corner and extreme temperature

Abstract: A circuit used for indicating process corner and extreme temperature mainly comprises a proportional to absolute temperature (PTAT) current source, a negative to absolute temperature (NTAT) current source, a constant to absolute temperature (CTAT) current source, a corner detector, a poly detector, an extreme temperature detector. The circuit can improve more power consumption without trade-off. In debug phase, the circuit can read out a state of a suspect sample and can run simulation check quickly to identify the real problem. In production phase, the circuit can easily read out at a processing station. In the mean time, a large quantity of data can be easily collected and analyzed.

Multi-factor advanced process control method and system for integrated circuit fabrication

Abstract: A method and system for integrated circuit fabrication is disclosed. In an example, the method includes determining a first process parameter of a wafer and a second process parameter of the wafer, the first process parameter and the second process parameter corresponding to different wafer characteristics; determining a variation of a device parameter of the wafer based on the first process parameter and the second process parameter; constructing a model for the device parameter as a function of the first process parameter and the second process parameter based on the determined variation of the device parameter of the wafer; and performing a fabrication process based on the model.

A low power consumption, low phase noise, and wide tuning range LC VCO with ACC

Abstract: A 4.8GHz LC voltage controlled oscillator (VCO) for WSN Applications is designed based on TSMC 0.18 µm RF CMOS process. The VCO adopts complementary differential negative resistance structure with switch resistor biasing which achieves good phase noise performance and realizing low power consumption. The 3-bit switch capacitor array provides wide tuning range and the 6-bit switch resistors array provides varied biasing current by auto current calibration (ACC) circuit. With a 1.8V supply voltage, the post-simulated result achieves 27.7% tuning range that can compensate the frequency deviation due to process corners. The post simulated phase noise is −119dBc/Hz@1MHz at frequency of 2.44GHz. The operating current of the VCO core is from 0.4mA to 3.3mA. Finally, the chip size of the VCO core is 0.3mm2 and the whole chip size is 0.8×1.2mm2 with testing buffer and pads.

Process variation sensitivity of the Rotary Traveling Wave Oscillator

Abstract: Rotary clocking is a low-power technology for multi-GHz clock generation and distribution. In this paper, a sensitivity analysis of the Rotary Traveling Wave Oscillator (RTWO) to process variations is presented based on a 90 nm technology. The analysis is focused on the effects of 1) multiple process corners, 2) power supply fluctuation, 3) chip temperature change, 4) the variations of the RTWO transmission line width and separation, on the operating frequency and power consumption of the RTWO. The individual analysis of these factors is presented as well as a Monte-Carlo based analysis to analyze the comprehensive effects of the process parameter variations and process corners. SPICE simulation results show that the RTWO exhibits a natural robustness to resist these on-chip variations.

VaROT: Methodology for Variation-Tolerant DSP Hardware Design Using Post-Silicon Truncation of Operand Width

Abstract: With increasing parameter variations in nanoscale technologies, computational blocks in Digital Signal Processing (DSP) hardware become increasingly vulnerable to variation-induced delay failures. These failures can significantly affect the Quality of Service (QoS) for a DSP chip leading to degradation in parametric yield. Existing post-silicon calibration and repair approaches, which rely on adaptation of circuit operating parameters such as voltage, frequency or body bias, typically incur large delay or power overhead in order to maintain QoS. In this paper, we present a novel low overhead approach of healing DSP chips by commensurately truncating the operand width based on its process corner. The proposed approach exploits the fact that critical timing paths in DSP data paths typically originate from the least significant bits (LSBs). This condition can also be satisfied by skewing the path delay distribution during logic synthesis or gate sizing. Hence, truncation of the LSBs, realized by setting them at constant values, can effectively reduce the delay of a unit, thereby avoiding delay failures. We also note that truncation of LSBs typically has minimal impact on QoS. Besides, efficient choice of truncation bits and values can minimize the impact on QoS. We propose appropriate design time modifications including insertion of low-overhead truncation circuit and gate sizing to maximize the delay improvement with truncation. Simulation results for a Discrete Cosine Transform (DCT) application at 45nm technology show large improvement in yield (41.6%) with up to 5X savings in power compared to existing healing approaches.

A sub-GHz UWB pulse generator for wireless implantable medical devices

Abstract: The design of a MOS-only pulse generator for sub-GHz Ultra-Wideband (UWB) biomedical communication is presented. The oscillator based pulse generator is capable of generating Binary Phase Shift Keying (BPSK) modulated pulses and is tunable in both frequency and output power. A varactor biasing circuit is developed that keeps the varactor bias voltage constant during oscillator startup and shutdown. The pulse occupies a bandwidth of 550 MHz. The center frequency can be controlled from 0.53 to 1.05 GHz and the digital gain control offers a 13.5 dB tuning range. For a 2.5 V supply and 1 MHz Pulse Repetition Frequency (PRF), the average power consumption ranges from 30 µW to 150 µW, depending on the pulse power controlled by the digital gain. The circuit performance is very robust over process corners, device mismatch and antenna reactance variations.

Structure and method for measuring electric property change of MOSFET (metal-oxide-semiconductor field effect transistor) device

Abstract: The invention provides a structure for measuring electric property change of MOSFET (metal-oxide-semiconductor field effect transistor) device, which comprises an active area, a grid electrode located on the active area, wherein the grid electrode is a resistor in Kelvin structure; two ends of the grid electrode have two polyresistor end points. The structure of the invention has the advantage that the influences of the grid length change, the gate oxide thickness change and the doping change to the MOSFET device are distinguished and determined; and the three process changes are the main factors of electrical fluctuations of device and are the primary parameters for building a monte carlo model and a corner mode of the device; the determination of the three process changes can lead the monte carlo model and the corner model to be more precise, which is quite important under the condition that the requirements on process corner models that is more than 90nm are higher and higher, and in favour of extracting a stress model of the device for placing numbers and distances of different virtual grid electrodes in more than 45nm of process. The invention further provides a method for measuring electric property change of MOSFET device.

Ultra Low Power CMOS Circuits Working in Subthreshold Regime for High Temperature and Radiation Environments

Abstract: We present three ultra-low-power CMOS circuits: a temperature sensor, a voltage reference and a comparator developed for an ultra-low-power microsystem (ULP-MST) aiming at temperature sensing in harsh environments. The microsystem has 3 main functions: detecting a user-defined temperature threshold T0, generating a wake-up signal that turns on a data-acquisition microprocessor (located in a safe area) above T0, and measuring temperatures above T0. To achieve ultra-low-power operation, the three CMOS circuits are implemented in Silicon-on-Insulator (SOI) CMOS technology and are optimized to work in the subthreshold regime of the transistors. Since our application is mainly for harsh environment (i.e. high temperature and radiation), the chip has been designed using a suitable 1-μm SOI-CMOS technology. Simulations have been performed over the different process corners to verify functionality after fabrication. The typical power dissipation at high temperature (up to 240°C) is less than 100 μW at 5 V supply ...

Method for generating simulation program with integrated circuit emphasis (SPICE) process corner model of field effect transistor

Abstract: The invention provides a method for generating a simulation program with integrated circuit emphasis (SPICE) process corner model of a field effect transistor In the method, the process variations of a wide channel region device and a short channel narrow channel region device are expressed by setting partitioning process corner parameters in the global model of the SPICE model The method comprises the following steps of: 1) measuring a current-voltage curve of a device and establishing a global model G; 2) determining the variation range of the process corner model; 3) selecting parameters DVT0, LVTH0, LU0, LK1, LVSAT and RDSW according to the size of a short channel; 4) selecting parameters K3, WVTH0, WK1 and WVSAT according to a small width size; 5) selecting parameters PVTH0, PVSAT and PU0 according to the size of the short channel and the small width size; and 6) integrating global parameters with local parameters so as to establish a corner model Compared with the prior art, the method has the advantages that: an excellent process corner model is generated, process variation can be reflected well and a circuit design can better reflect the variation

Method to achieve constant slew rate (over process corners) for an output buffer

Abstract: An apparatus comprising a first circuit, a state machine, a compare circuit and a calibration circuit. The first circuit may be configured to generate a slew rate control signal and a calibration signal in response to (i) a plurality of control bits and (ii) an operation signal. The state machine may be configured to generate the operation signal and a plurality of intermediate control signals in response to (i) a compare signal and (ii) clock signal. The compare circuit may be configured to generate the compare signal in response to (i) a reference voltage and (ii) a capacitance signal. The calibration circuit may be configured to generate the capacitance signal in response to (i) the calibration signal and (ii) the plurality of intermediate control signals.

0.18um low voltage 12-bit successive-approximation-register analog-to-digital converter (SAR ADC)

Abstract: This paper presents a 0.18um process Successive-Approximation Register Analog-to-Digital Converter (SAR ADC) design that can operate at a low voltage of minimum 1.4V across process corners and temperature with the power consumption of less than 100uW. The design comprises three main blocks namely a fully differential latched comparator, binary-weighted capacitors Digital-to-Analog Converter (DAC) and a SAR digital control logic module. The SAR ADC was designed to work at a minimum of 1.4V to cater to the 1.5V AA-battery +/−10% and accepts a maximum clock frequency of 500 kHz. In order to reduce the current consumption, this design uses the capacitors in the DAC as the sample-and-hold (S/H) component, together with a hybrid DAC architecture. The pre-amp used before the comparator has folded-cascode configuration to enable it to work at a low voltage level and differential outputs to account for noise cancellation. This circuit was designed using Silterra C18G 0.18um process.

Heavy Ion Characterization and Monte Carlo Simulation on 32 nm CMOS Bulk Technology

Abstract: Heavy ion experimental test results carried out on static random-access memories (SRAMs) manufactured in bulk complementary metal-oxide semiconductor (CMOS) 32 nm are compared to Monte Carlo simulations. Additional simulation capabilities allow for insight in heavy ion cross-section variations as a function of temperature, power supply voltage, and process corners. Monte Carlo simulations of a radiation-hardened-by-design flip-flop based on a dual-interlocked storage cell latch have been performed and show similar sensitivities for 65 nm and 32 nm technologies. Finally, for the first time, the heavy-ion cross-section of the 20 nm bulk CMOS SRAMs is anticipated by simulation by using the latest available technology data.

A high-performance low-power highly manufacturable embedded DRAM technology using backend hi-k MIM capacitor at 40nm node and beyond

Abstract: A highly manufacturable embedded DRAM technology at 40nm node is presented. This report provides the characterization data of 128Mbit embedded DRAM test vehicle fabricated by 40nm eDRAM 200MHz low power process. The test vehicle is composed of 32 macros and each macro unit is 4Mb with configuration 32k×128 bits. The process is cost effective and compatible to our low power Logic core process with three additional critical masks to the base process. The DRAM memory cell consists of a high performance pass gate transistor and a metal-insulator-metal (MIM) storage capacitor with a cell size of 0.0583 um2 (< 1/4 of SRAM 0.242 um2) and small macro size of 0.145 mm2 per Mega bits (Mb). The stacked cell capacitor is formed using low temperature processed high-k dielectrics to achieve sufficient storage capacitance in DRAM cell. Low cell device leakage below 20 fA/cell at 105°C with silicided node process coupled with the high-k storage capacitance. The macro design for random access speed can operate from 25MHz to 200 MHz comparable to 6T SRAM. It has built-in ECC parity generation and correction circuits with memory storage space used for storing parity bits. The characterization is based on 200MHz, covering Vcc+/−15% at 125°C/ 105°C/ 25°C/ −40°C. Process corner skew includes core device corners TT/FS/SF/FF/SS and fast/slow cell device. Highly manufacturing yield of 128Mb macro is achieved to demonstrate the maturity of technology. The excellent cosmic ray (neutron) soft error rate (SER) performance of less than 4FITs/Mb is also achieved. The integration technologies can be applicable to the future embedded DRAM in 28nm, 20nm node and beyond.

A novel adaptive reverse body bias technique to minimize standby leakage power and compensate process and temperature variations

Abstract: With technology scaling down, leakage power plays an increasingly important role in low power logic design and becomes more susceptible to process and temperature fluctuations. In this paper, a novel adaptive body bias technique is proposed to minimize leakage power and compensate process and temperature variations of nanoscale CMOS VLSI circuits in standby mode. Taking sub-threshold current, gate leakage and band-to-band current into consideration, the optimal value of body bias is determined by comparing the drain leakage currents of two off-state replica clusters applying two slight different body bias voltages. The proposed circuit was implemented using 90nm CMOS technology and applied on ISCAS85 benchmark circuits to validate its efficiency in different process corners (slow, typical and fast process) and operating temperatures (ranging from −40°C to 85°C). Simulation results indicate that the maximum standby leakage power reduction percentage is 93.94%. The proposed circuit can adaptively adjust the body bias to its optimal value during the whole standby period, which results in considerable reduction of leakage power and effective compensation of process and temperature variations.