Showing papers on "Process corners published in 2012"

RC corner solutions for double patterning technology

Abstract: A method includes selecting a process corner, determining model parameters for forming an integrated circuit, and generating a file using the model parameters for the process corner. The generating the file is performed using a computer. The file includes at least two of a first capacitance table, a second capacitance table, and a third capacitance table. The first capacitance table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks including the layout patterns shift relative to each other. The second capacitance table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The third capacitance table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other.

Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits

Abstract: Worst-case design uses extreme process corner conditions which rarely occur. This limits maximum speed specifications and costs additional power due to area over-dimensioning during synthesis. We present a new design synthesis strategy for digital CMOS circuits that makes use of forward body biasing. Our approach renders consistently a better performance-per-area ratio by constraining circuit over-dimensioning without sacrificing circuit performance. An in-depth analysis of the body-bias-driven design theory is provided. It is complemented by an algorithm that enables fast reconstruction of the area-clock period tradeoff curve of the design. We validated these new concepts through industrial processor designs in 90-nm low-power CMOS. For standard- Vth implementations, we observed performance-per-area improvements up to 40%, area and leakage reductions up to 30%, and dynamic power savings of up to 10% without performance penalties as a benefit from our proposed body-bias-driven design strategy. The benefits are larger for high-Vth implementations. In this case, we observed performance-per-area improvements up to 90%, area and leakage reductions up to 40%, and dynamic power savings of up to 25% without performance penalties.

Spatial estimation of wafer measurement parameters using Gaussian process models

Abstract: In the course of semiconductor manufacturing, various e-test measurements (also known as inline or kerf measurements) are collected to monitor the health-of-line and to make wafer scrap decisions preceding final test. These measurements are typically sampled spatially across the surface of the wafer from between-die scribe line sites, and include a variety of measurements that characterize the wafer's position in the process distribution. However, these measurements are often only used for wafer-level characterization by process and test teams, as the sampling can be quite sparse across the surface of the wafer. In this work, we introduce a novel methodology for extrapolating sparsely sampled e-test measurements to every die location on a wafer using Gaussian process models. Moreover, we introduce radial variation modeling to address variation along the wafer center-to-edge radius. The proposed methodology permits process and test engineers to examine e-test measurement outcomes at the die level, and makes no assumptions about wafer-to-wafer similarity or stationarity of process statistics over time. Using high volume manufacturing (HVM) data from industry, we demonstrate highly accurate cross-wafer spatial predictions of e-test measurements on more than 8,000 wafers.

Experimental characterization of process corners effect on SRAM alpha and neutron Soft Error Rates

Abstract: This paper shows alpha and neutron experimental Soft Error Rate characterization of a SRAM test vehicle processed with different process corners in order to emulate the variability encountered in volume production. It allows assessing large variability effects with few samples that are compatible with accelerated SER testing. This allows investigating the effect of variability in mass-production on soft error rate of deca-nanometric technologies.

Tier-adaptive-voltage-scaling (TAVS): A methodology for post-silicon tuning of 3D ICs

Abstract: This paper presents tier-adaptive-voltage-scaling (TAVS) as a post-silicon tuning methodology for improving parametric yield of 3D integrated circuits considering die-to-die and within-die process variations. The TAVS methodology senses process corners of individual tiers using on-tier delay sensors and adapt the supply voltage of each tier. The overall TAVS architecture is presented and the circuit issues associated with design of 3D level shifters are discussed. Circuit level simulation and statistical analysis of the TAVS architecture in predictive 45nm technology show the possibility of 26%–39% reduction in chip delay distribution.

A 1.2V 2-bit phase interpolator for 65nm CMOS

Abstract: We present a digital phase interpolator (PI) design for 65nm CMOS that avoids conventional analog structures, accurately achieves 2-bits phase resolution across a range of rise time and input delays from t rise : 48ps → 200ps using a ratio t rise /t delay of at least 1 or greater. Increased accuracy is available for certain rise times using ratios increasing between 1 and 10 as verified by simulations across process corners using extracted parasitic capacitances but ignoring MOSFET mismatch effects. Power consumption was estimated at 30nW/MHz → 38nW/MHz across a range of process variation corners in these operating conditions. Monte Carlo simulations across process and MOSFET mismatch conditions show large variations in estimated accuracy. Monte Carlo trials show the PI achieves a worst case DNL error (mean±3σ) of 1.06 LSB using t rise /t delay ratio of 5.3 and 48ps rise time, and a worst case DNL error (mean ±2σ) of 0.49 LSB for t rise /t delay ratio of 4 and 84ps rise time.

A compact low-power supply-insensitive CMOS current reference

Abstract: A simple low-power current reference using dual-threshold MOS transistors is introduced. The area required for this reference is small and the sensitivity of the output current to the supply voltage is low. Simulation results show that an implementation of this current reference in a TSMC 0.18um CMOS process with a 1.8V power supply is constant to within ±1.25% over the temperature range of −10°C to 100°C. In this implementation, the active area is 86 µm2, the power dissipation is 72µW, and the worst process corner nonlinearity due to temperature variations is bounded by ±4.16%.

Comparison of modeling techniques in circuit variability analysis

Abstract: Three nonlinear reduced-order modeling approaches are compared in a case study of circuit variability analysis for deep submicron complementary metal-oxide-semiconductor technologies where variability of the electrical characteristics of a transistor can be significantly detrimental to circuit performance. The drain currents of 65 nm N-type metal-oxide-semiconductor and P-type metal-oxide-semiconductor transistors are modeled in terms of a few process parameters, terminal voltages, and temperature using Kriging-based surrogate models, neural network-based models, and support vector machine-based models. The models are analyzed with respect to their accuracy, establishment time, size, and evaluation time. It is shown that Kriging-based surrogate models and neural network-based models can be generated with sufficient accuracy that they can be used in circuit variability analysis. Numerical experiments demonstrate that for smaller circuits, Kriging-based surrogate modeling yields results faster than the neural network-based models for the same accuracy whereas for larger circuits, neural network-based models are preferred as, in all metrics, better performance is obtained. Within-die variations for an XOR circuit are analyzed, and it is shown that the nonlinear reduced-order models developed can more effectively capture the within-die variations than the traditional process corner analysis. Copyright © 2011 John Wiley & Sons, Ltd.

A 16Gbps low power self-timed SerDes transceiver for multi-core communication

Abstract: This paper presents a modified design for a self-timed SerDes transceiver that was recently published [1]. The new architecture overcomes the main problems that arise in [1], while offering the same advantages. Resistive termination is used instead of source matching to eliminate the need for Manchester coding in [1], this resistive termination increased the data rate to be 16Gbps compared to 12Gbps in [1]. Moreover, resistive termination removed the limitation on the minimum operating frequency that existed in [1], solving a lot of problems at the slow process corners. A single ended transmission line is used instead of the differential transmission line in [1]. A calibration circuit is implemented to control the switching threshold of the detector at the receiver side to account for voltage and process variations. The SerDes transceiver is implemented for a 3mm long on-chip transmission line in 65nm TSMC CMOS technology, which is the same as [1]. The total power consumed in the Tx/Rx pair with the transmission line is 18.1mWatt, compared to 15.5mWatt in [1]. The proposed architecture have the same advantages in [1] of being self timed, eliminating the need for complex power hungry blocks such as Clock and Data Recovery (CDR) at the receiver, and being insensitive to jitter accumulated during transmission.

Fully digital low-power self-calibrating BPSK demodulator for implantable biosensors

Abstract: In this paper we present a novel all digital binary phase shift keying (BPSK) demodulator dedicated implantable biosensor. This demodulator offers the advantages of ultra-low power and low complexity structure which are very essential to develop wireless miniaturized implantable devices. As the continuation of our research approach to implement a glucose sensor implanted under skin, herein, we address the design and analysis of a demodulator integrated in a CMOS chip along with other required building blocks. In order to minimize the effect of transmitter frequency changes and to enhance the circuit robustness a digital self-calibration technique is also proposed. Simulation results show that the demodulator can tolerate a relatively large frequency shift of at least ±80% around the centre frequency in all process corners. The power consumption of the demodulator at a data transmission rate of 16 Mbps and a supply voltage of 1.8 V is as low as 27µW.

Methodology of grading reliability and performance of chips across wafer

Abstract: A system and method sorts integrated circuit devices. Integrated circuit devices are manufactured on a wafer according to an integrated circuit design using manufacturing equipment. The design produces integrated circuit devices that are identically designed and perform differently based on manufacturing process variations. The integrated circuit devices are for use in a range of environmental conditions, when placed in service. Testing is performed on the integrated circuit devices. Environmental maximums are individually predicted for each device. The environmental maximums comprise ones of the environmental conditions that must not be exceeded for each device to perform above a given failure rate. Each integrated circuit device is assigned at least one of a plurality of grades based on the environmental maximums predicted for each device. The integrated circuit devices are provided to different forms of service having different ones of the environmental conditions based on the grades assigned to each device.

An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation

Abstract: A multiple supply voltage scheme is an emerging approach to reduce power dissipation. The scheme requires a level converter as a bridge for different voltage domains. Conventional level converters fail to work in sub-threshold region due to the pull-down devices and the pull-up devices operate in sub-threshold and super-threshold region respectively. By employing diode-connected PMOS transistors, multiple-threshold-voltage CMOS (MTCMOS), and stack leakage reduction techniques, the proposed cross-coupled level converter achieves small propagation delay, low power consumption, and best power-delay-product (PDP) performance. Also, the reverse short channel effect is utilized to provide our level converter better process/thermal variation immunity. We also propose a dual edge-triggered explicit-pulsed level-converting flip flop (LCFF) concept combining a DCVSPG latch and our level converter. The proposed cross-coupled level converter is designed using TSMC 65nm bulk CMOS technology. It functions correctly across all process corners for a wide input voltage range, from 150mV to 1V. The level converter has a propagation delay of 52ns and a power dissipation of 21nW when the input voltage is 150mV.

Towards Process Variation-Aware Power Gating

Abstract: This paper presents a power gating design that considers process variation for proper wakeup control. First, the surge current constraint is examined and refined for a simpler and more realistic view of inter-module reliability. Following that, several circuits are proposed on top of a delay chain to adapt the timing control of power switches to process variations. Experimental results show that the proposed design is able to track process variation such that the surge current and the wakeup time are both kept to expectation in all process corners.

Validation signature testing: a methodology for post-silicon validation of analog/mixed-signal circuits

Abstract: Due to the use of scaled technologies, high levels of integration and high speeds of today's mixed-signal SoCs, the problem of validating correct operation of the SoC under electrical bugs and that of debugging yield loss due to unmodeled multi-dimensional variability effects is extremely challenging. Precise simulation of all electrical aspects of the design including the interfaces between digital and analog circuitry, coupling across power and ground planes, crosstalk, etc., across all process corners is very hard to achieve in a practical sense. The problem is expected to get worse as analog/mixed-signal/RF devices scale beyond the 45nm node and are more tightly integrated with digital systems than at present. In this context, a post-silicon validation methodology for analog/mixed-signal/RF SoCs is proposed that relies on the use of special stimulus designed to expose differences between observed DUT behavior and its predictive model. The corresponding error signature is then used to identify the likely "type" of electrical bug and its location in the design using nonlinear optimization algorithms. Results of trial experiments on RF devices are presented.

Design and analysis of a new sub-threshold DTMOS SRAM cell structure

Abstract: In this paper, we propose a novel dynamic threshold (DTMOS) based fully differential ten-transistor (10T) SRAM (Static Random Access Memory) cell suitable for sub-threshold operation. The structure has two inverters in addition to the conventional 6T standard cell. It provides better read current, increased read and hold static noise margins (SNM) and improved write time compared to a recently proposed sub-threshold SRAM cell. The stability of sub-threshold DTMOS SRAM to process variations is also investigated. The robust dynamic threshold based memory cell exhibits built-in process variation tolerance that gives tight SNM distribution across the process corners.

Integrated circuit manufacturing for low-profile and flexible devices

Abstract: A process for manufacturing low-profile and flexible integrated circuits includes manufacturing an integrated circuit on a wafer having a thickness larger than the desired thickness. After the integrated circuit is manufactured the integrated circuit may be released with a portion of the wafer leaving a remainder of the bulk portion of the wafer. A second integrated circuit may be manufactured on the remainder of the wafer and the process repeated to manufacture additional integrated circuits from a single wafer. The integrated circuits may be released from the wafer by etching vias through the integrated circuit and into the wafer. The via may be used to start an etch process inside the wafer that undercuts the integrated circuit separating the integrated circuit from the wafer.

Design of low power, low jitter DLL tested at all five corners to avoid false locking

Abstract: A modified Phase Selection Circuit, a modified Phase Frequency Detector and a modified Voltage Controlled Delay Line is proposed to improve the Delay Locked Loops (DLL) locking time, lock range and the jitter performance. Also the DLL presented in this paper has a wide-range frequency operation. A modified Phase Selection circuit is designed in order to operate DLL over wide frequency range and completely solve the false locking problem. Also a Modified Phase Frequency detector circuit has been designed to reduce the phase error as well as dead-zone situation. The proposed DLL design is simulated in Cadence Spectre using TSMC 180nm CMOS Technology and 1.8V power supply voltage operate correctly when the input clock frequency is changed from 84 to 800MHz and generate ten-phase clocks within just one clock cycle. The simulation is performed for all five process corners. The DLL consumes maximum power of 6.85mW at 800MHz working at FF corner, whereas, the maximum peak-to-peak jitter is 4ps at 84MHz working at FS corner. Both maximum power and jitter is measured at temperature and voltage of −40°C and 1.98V.

Semiconductor element, memory circuit, integrated circuit, and driving method of the integrated circuit

Abstract: A novel semiconductor element contributing to an increase in circuit scale is provided. In the semiconductor element, two different electrical switches are formed using a single oxide semiconductor layer. For example, in the semiconductor element, formation of a channel (a current path) in the vicinity of a bottom surface (a first surface) of the oxide semiconductor layer and formation of a channel in the vicinity of a top surface (a second surface) of the oxide semiconductor layer are independently controlled. Therefore, the circuit area can be reduced as compared to the case two electrical switches are separately provided (for example, the case where two transistors are separately provided). That is, a circuit is formed using the semiconductor element, whereby an increase in the circuit area due to an increase in circuit scale can be suppressed.

Bitline Leakage Current Compensation Circuit for High-Performance SRAM Design

Abstract: The leakage current existing in the bitline of SRAM has attracted more and more concerns for the operation of high-performance SRAM design, especially with the decrease of the threshold voltage of the transistor for high-performance demand, the leakage current would increase exponentially. The increased leakage current may slowdown the performance of the read operation of SRAM because the existence of the leakage current in the bitline may postpone the time to resolve the sufficient differential bitline voltage for SA to sense correctly. In this paper, a new bitline leakage current compensation circuit has been proposed. Different from the traditional technique, the proposed bitline leakage current compensation circuit cancels the "pre-determined" leakage current compensation process. Therefore, it dodges the dilemma where the performance of the SRAM may be degraded in some circumstances if the bit-line leakage current is compensated pre-determinedly. The simulation results show that by adopting the proposed compensation circuit, the time needed to develop 1/2 VDD can be reduced by almost 126.4% under the tt process corner.

Digital pulse width modulator based on digital delayed-locked loop (DLL)

Abstract: The invention discloses a digital pulse width modulator based on a digital delayed-locked loop (DLL). The digital pulse width modulator comprises: a frequency division circuit, a DLL oscillation loop circuit, a reset signal generation circuit and a PWM output logic circuit. By using inputting a high frequency clock signal fs, the DLL oscillation loop triggers a oscillation loop to perform concussion outputting a 2 channel signal and then the signal is sent to the reset signal generation circuit. The reset signal generation circuit combines the input fs and a duty ratio command signal of mbits so as to generate a pulse signal PWM_clr. Under an effect of post-stage PWM output logic circuit, the PWM signal is generated so as to be taken as the output of the system. The DLL oscillation loop circuit uses a programmable delay unit (PDU) to real-timely track the input signal so that the effect of outputting a good pulse width modulation wave under different process corners and differentworking environments can be achieved. By using the digital pulse width modulator of the invention, areas needed by a chip can be minimized to a larger degree and costs of chip development can be saved.

Design of an Ultra-Low-Power multi-stage AC/DC voltage rectifier and multiplier using a fully-automated and portable design methodology

Abstract: A fully-automated and portable design methodology has been developed based on an efficient model and a gradient's method to optimize an ULP (Ultra Low Power) AC-DC multi-stage rectifier through the overall design window in a practical design time. Innovative ULP diodes featuring two CMOS transistors are modeled and used to reduce leakage. The diode model includes parasitic capacitances, thus taking into account DC and AC behavior for various frequencies and voltage amplitudes. A 3-stage rectifier taking a 1 Vpp input sinusoidal signal at 13.56 MHz and providing a 10 μA load current has been designed in 250 nm bulk CMOS technology with 72% power conversion efficiency and 1.99 V output voltage. Robust design decisions with respect to process corner variations have been reached with this methodology and are also presented.

Methods and apparatus for performing statistical static timing analysis

Abstract: A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners using a static timing analysis module, and estimating performance of the circuit at a predetermined confidence level based on results of the statistical analysis during an automated design flow of the circuit without using libraries at the predetermined confidence level.

High Precision Low Temperature Coefficient Current Reference with Resistor Compensation

Abstract: In order to improve temperature characteristics and precision of current reference, a novel resistor compensated current reference based on bandgap voltage reference with trimming network is proposed in this paper. By introducing the combination of 2nd order resistor and transmission gate whose temperature characteristics compensate that of bandgap voltage reference, lower temperature coefficient has been achieved. This circuit is implemented using HHNEC 0.35um BCD process with 3.3V power supply. Simulation results for the proposed current reference show the worst temperature coefficient of 15.25ppm/°C and the best temperature coefficient of 5ppm/°C over a temperature range from -45°C to 85°C. With trimming network, an output current variation of 1.4‰ is achieved among process corners. On the premise of not introducing high-order curvature compensated to bandgap which increase circuit complexity, this circuit put forward a new thought for the design of current reference. Keywords-Current reference, Resistor compensation, Trimming network, Temperature coefficient

A hybrid and adaptive model for predicting register file and SRAM power using a reference design

Abstract: This paper presents a predictive SRAM power model that reduces the changes required to adapt existing models to handle new circuit topologies, process corners, and design space exploration. Analytical equations model the impact of varying common characteristics such as bit-width, entries, segmentation, gating, and sizing while topology specific characteristics are captured empirically from a reference design. On distinct topologies of multi-port read, single- and dual-ended writes, this approach demonstrates an error of 5% and 7% for leakage and dynamic power respectively. We show that for a specific topology, any reference configuration can be used for accurate prediction.

Performance and Variability Trade-off With Gate-to-Source/Drain Overlap Length

Abstract: The impact of gate-to-source/drain overlap length on performance and variability of 65 nm CMOS is presented. The device and circuit variability is investigated as a function of three significant process parameters, namely gate length, gate oxide thickness, and halo dose. The comparison is made with three different values of gate-to-source/drain overlap length namely 5 nm, 0 nm, and -5 nm and at two different leakage currents of 10 nA and 100 nA. The Worst-Case-Analysis approach is used to study the inverter delay fluctuations at the process corners. The drive current of the device for device robustness and stage delay of an inverter for circuit robustness are taken as performance metrics. The design trade-off between performance and variability is demonstrated both at the device level and circuit level. It is shown that larger overlap length leads to better performance, while smaller overlap length results in better variability. Performance trades with variability as overlap length is varied. An optimal value of overlap length of 0 nm is recommended at 65 nm gate length, for a reasonable combination of performance and variability.

Reference voltage buffer circuit

Abstract: The utility model provides a reference voltage buffer circuit, belonging to the integrated circuit field. The reference voltage buffer circuit comprises a first MOS (Metal Oxide Semiconductor) transistor and a second MOS transistor both driven by a first operational amplifier, and a current mirror circuit, wherein the current mirror circuit is connected with the first MOS transistor and the second MOS transistor; and the source of the second MOS transistor serves as a reference voltage output end. The current mirror circuit in the reference voltage buffer circuit provided by the utility model is capable of providing accurately matched current, thereby generating an accurately matched circuit working point, and solving the technical problem that the output voltage is incapable of well following the input voltage due to the change of factors such as resistance error, mismatch of two resistors, power supply voltage, process corner, temperature and the like in the reference voltage buffer circuit in the prior art. The output voltage of the reference voltage buffer circuit provided by the utility model is capable of accurately following the input voltage.

Product/device reliability correlations for low-power applications

Abstract: Summary form only given. Portable products such as cellular phones, laptop or tablet computers have critical power consumption limitations. Highly scaled 28nm CMOS technologies and beyond show high variability in process which impacts reliability. The high process, temperature and reliability variability pose significant power consumption challenges at product level. Power consumption at process corners can vary as much as 50%. In order to optimize high-speed logic circuit designs for low power needs, we need to accurately predict device to product aging across process, temperature and voltage corners. Understanding the impact of process and temperature variability on device/circuit aging and its correlation to product level reliability results is the focus of this talk. We compare the device/circuit aging for 28nm CMOS technology with SiON vs high-k gate dielectrics at different process corners SS, TT and FF. The talk offers insights into optimizing high performance designs at low power for portable product applications.

A high-precision ultra-low-power hysteretic voltage detector for energy harvesting system

Abstract: A high-precision ultra-low-power, hysteretic voltage detector (HVD) featuring temperature and process insensitivity is presented in this paper. In order to improve its thermal stability, a temperature-independent current is generated by a special voltage-controlled current source. The current is compared with a reference current to determine the start-up voltage of hysteresis window. And a Schmitt inverter is served to provide the hysteresis window. Besides, a current pre-amplifier is developed to enhance the HVD's response to small changes of the detected voltage. The HVD is designed and fabricated in SMIC 0.18 µm CMOS process. The simulation results show that its hysteresis window is about 0.02V. And the sensitivity to temperature and process corners are about 347ppm/°C and −1.5%∼2.3% respectively. In addition, the HVD can response precisely to as low as 1mV variation around the switching voltage. The total power consumption of this HVD is only 840nW at 1.8V supply voltage.