Showing papers on "Process corners published in 2015"

Using Wafer Map Features to Better Predict Die-Level Failures in Final Test

Abstract: In semiconductor manufacturing, wafer fabrication is followed by chip assembly where individual dies are assembled as a packaged chip. In between, dies are tested in terms of their electrical properties and those which fail to pass the “wafer test” are filtered out. However, some faulty dies pass the test and cause a packaged chip to fail in the final test. The inaccuracy of the wafer test leads to waste in manufacturing time and cost. In this paper, we propose to predict the result of the final test at the die-level before assembly using wafer test items and four derivations concerning wafer map features: 1) distance of the die from the wafer center; 2) previous final yield at the die position; 3) wafer test fail rate for the adjacent dies; and 4) abnormalities of the wafer map pattern. We build prediction models with these variables using a random forest algorithm. Preliminary experimental results on actual data show that the use of these derived variables improves the prediction performance with a statistical significance, thus merits further investigation.

Entropy and Energy Bounds for Metastability Based TRNG with Lightweight Post-Processing

Abstract: On-chip True Random Number Generators (TRNG) are important cryptographic primitives in a variety of applications. In advanced CMOS process technologies, intra-die variations in transistor parameters bias the TRNG and degrade the statistics of the bit stream generated. In this work, we present a stochastic model for metastability based TRNG circuit incorporating both the impact of intra-die variations and thermal noise. The stochastic model is used to estimate the expected entropy out of a TRNG at a given process corner for variations in channel length and threshold voltage. We use the stochastic model to study the impact of variations on three lightweight post-processing techniques: von Neumann corrector, XOR function, and PRESENT cipher. The expected bit rate out of von Neumann corrector, number of XOR stages required for entropy extraction and the number of iterations for using PRESENT encryption are estimated for various process corners using the probabilistic entropy values. These analyses are further extended to different device sizing and operating voltage to explore the optimum trade-off between entropy extraction and energy overhead. A combination of HSPICE circuit simulation using 32 nm Predictive Technology models and stochastic modeling in MatLab show that XOR function and von Neumann corrector have an energy overhead ranging from 0.012pJ/bit to 0.15pJ/bit at the cost of decreased yield and bit-rate respectively. PRESENT cipher provides robust entropy extraction by increasing the number of encryption iterations from 1 for $\mu/\sigma(Leff) to 3 for $\mu/\sigma(Leff)>8\%$ . With a maximum of 2.52pJ/bit PRESENT provides a more energy efficient solution compared to AES for entropy extraction in power constrained applications.

Near-zero dead zone phase frequency detector with wide input frequency difference

Abstract: An all-digital phase frequency detector design capable of accepting an infinite range of input frequency differences and [0 2π] radians input phase difference is presented. The proposed phase frequency detector design minimises the dead zone, supresses unwanted output glitches, achieves a high maximum operating frequency, can drive high-capacitive loads and avoids differential outputs. The proposed phase frequency detector takes advantage of a fast reset operation from modified tristate inverters acting as a D flip-flop. Simulation results indicate that the design can detect input phase differences as small as 750 fs apart for all process corners at input operating frequencies of 38 kHz–2.5 GHz in 1.2 V, 90 nm CMOS technology.

Impact of time-zero and NBTI variability on sub-20nm FinFET based SRAM at low voltages

Abstract: BSIM-CMG based HSPICE framework is developed for simulating time-zero and Negative Bias Temperature Instability (NBTI) variability of SRAM performance parameters. Time-zero variability of Read Static Noise Margin, Hold Static Noise Margin and Flip-Time for different process corners are simulated. Models used for SPICE simulation are foundry qualified sub-20nm FinFET for two types of 6T SRAM cells, HighSpeed and High-Density cells. The Impact of stochastic BTI for DC and AC activity stress on these parameters are studied for relevant worst-case process corner. The impact of Vdd reduction on time-zero and post-BTI SRAM parameter variability is also studied. Critical failure situations are identified.

CMOS current reference with temperature compensation

Abstract: Current reference is an essential building block in all analog-mixed signal integrated circuits. Basic current references are sensitive to temperature variations, and may vary up to ±30% for a temperature range −30 °C to 135°C. This paper, suggests a technique of combining two current reference models with complementary temperature characteristics, to improve stability of the reference current to 1.14% for the full range of temperature variation; and a dynamic variation which is below 57ppm/ °C. The circuit is designed for a current reference of 5µA for 180nm CMOS technology and Physical design (Layout) is simulated for a temperature range of −30°C to 135 °C across process corners.

Gain enhanced high frequency OTA with on-chip tuned negative conductance load

Abstract: An enhanced gain, high frequency, operational transconductance amplifier (OTA) architecture using negative conductance load to cancel its output parasitic conductance across process, voltage, and temperature (PVT) variations without the need of any off-chip intervention is proposed. Simulation results of a prototype transconductor in 0.13μm CMOS process over process corners, 100°C temperature range, and ±10% supply voltage variations show that the DC gain is enhanced from 14dB to 48dB when cancellation using negative conductance is incorporated. A minimum DC gain of 34dB and an average DC gain of 46dB is observed over 500 Monte-Carlo mismatch runs. The OTA has a unity gain bandwidth (UGB) of 20GHz.

A Fully On-Chip PT-Invariant Transconductor

Abstract: This brief presents a novel process and temperature (PT)-invariant transconductor, fabricated and tested in 180-nm CMOS technology. It uses a novel bias circuit for implementing a PT-invariant transconductor using a MOSFET in triode region. Measurements show that the transconductance varies only by ±3.4% across 18 fabricated chips and over temperatures ranging from 25 °C to 100 °C. Simulations show that variation of the transconductance across process corners is ±6.7% and across temperature range of 0 °C to 100 °C is ±1.6%. The proposed PT-invariant transconductor has the minimum variation among the fully on-chip transconductors reported so far. The proposed circuit consumes 136 $\mu $ W of power.

Minimizing the number of process corner simulations during design verification

Abstract: Integrated circuit designs need to be verified in simulation over a large number of process corners that represent the expected range of transistor properties, supply voltages, and die temperatures. Each process corner can require substantial simulation time. Unfortunately, the required number of corners has been growing rapidly in the latest semiconductor technologies. We consider the problem of minimizing the required number of process corner simulations by iteratively learning a model of the output functions in order to confidently estimate key maximum and/or minimum properties of those functions. Depending on the output function, the required number of corner simulations can be reduced by factors of up to 95%.

An improved voltage bandgap reference with high-order curvature compensation

Abstract: This paper presents an improved bandgap reference (BGR) with high-order curvature compensation. By adding a second-level operational tranconductance amplifier (OTA) with feedback, fully improve the correctness of hypothesises in paper [3]. In addition, the output voltage reference can be further compensated than the conventional high-order BGR from theoretical analysis and simulation results. Through the comparison and analysis with conventional compensation BGR, the proposed bangap structure has a smaller temperature coefficient of output voltage reference. Finally the simulation results based on 0.1μm CMOS process with 1.5V supply voltage indicate that the temperature coefficient of the proposed reference is 25.5ppm/°C during the temperature range (−30°C∼120°C) over different process corners.

Simple high-resolution CMOS phase frequency detector

Abstract: A high-resolution phase frequency detector (PFD) is designed for high-frequency signal detection and low jitter phase locked loop applications. The proposed PFD eliminates the reset path delay and usage of any latches, minimise the dead zone to near zero by generating narrow pulses at each input rising edge. In addition, the designed PFD completely removes unwanted output glitches, accepts inputs with a large difference in frequency, and also has the ability to drive a large capacitive load with minimal impact on performance. The proposed PFD is designed in 90 nm CMOS technology with a 1.2 V power supply. Simulation results indicate that the proposed design can operate over a wide range of frequencies from 10 kHz to 6 GHz and can detect phase differences for inputs as small as 125 fs for all frequencies of operation and for all process corners. The simulated power consumption is 75 µW at 166.6 MHz with an input phase difference of 125 fs.

ESD protection clamp with active feedback and mis-trigger immunity in 28nm CMOS process

Abstract: Data Converters in 28nm CMOS processes have the need to support higher voltage power supply domains in addition to the more traditional core and I/O voltages. In this work a new supply clamp architecture is proposed which ensures a reliable low leakage performance at the higher supply voltages (2.5V/3.3V). An active feedback network is designed into the supply clamp architecture to ensure uniform clamping during the duration of the ESD event. Miss-trigger immunity and over voltage protection is additionally incorporated to ensure reliable functionality up to 3.3V and across all the process corners.

Method for analyzing interconnect process variation

Abstract: A method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided. First descriptions of parasitic RC elements in an interconnect structure of an IC are generated. The first descriptions describe the parasitic RC elements respectively at a typical process corner and a peripheral process corner. Sensitivity values are generated at the peripheral process corner from the first descriptions. The sensitivity values respectively quantify how sensitive the parasitic RC elements are to process variation. The sensitivity values are combined into a second description of the parasitic RC elements that describes the parasitic RC elements as a function of a process variation parameter. Simulation is performed on the second description by repeatedly simulating the second description with different values for the process variation parameter.

Design of area efficient and low power bandgap voltage reference using sub-threshold MOS transistors

Abstract: Voltage references are very essential components of analog VLSI circuits A reference source is expected to remain constant against supply voltage, temperature and process parameter variations The forward voltage drop across junction diode exhibits a negative temperature dependence of about 2mV/°C, which is compensated by a suitably scaled proportional to absolute temperature (PTAT) component to obtain the bandgap voltage reference The conventional bandgap voltage reference constituting of bipolar transistors and opamp will consume more power and area In order to overcome this drawback, we propose a novel design of low power bandgap voltage reference that substitutes sub-threshold MOS transistors in place of bipolar transistors and a regenerative bias circuit in place of opamp The circuit works on a supply of 1V (±10%) and within a temperature range of −40°C to 125°C The circuit is designed to give a constant voltage of 5463mV with a temperature coefficient of 144ppm/°C The proposed circuit occupies an area of 00094mm2 which is very less as compared to commonly used architectures The designed architecture is tested across all the process corners [SS, FF, TT, SNFP and FNSP] in 180nm technology using CADENCE tool (UMC180)

2.64 pJ reference-free power supply monitor with a wide temperature range

Abstract: Power supply noise in current nanometer technologies represents a growing risk, specially because of the uncertainties it produces in the critical paths delays which can result in erroneous computations. To tackle with these issues and to have a better power management, power supply monitors are necessary. Traditional approaches use an external reference or are very sensitive to temperature and process variations. In this work we propose a monitor that works without an external reference and is hardened against thermal and process variations. The sensor was designed in the 40 nm CMOS technology node, operating at 1.1 V and has been validated for a temperature range of -40 °C to 125 °C covering all process corners. The sensor is able to detect voltage fluctuations of at least 45 mV, wider than 300 ps in the worst technology corner with a maximum latency of 600 ps and an energy consumption per measurement of 2.64 pJ.

Design of 900 Mhz AC to DC Converter Using Native Cmos Device of TSMC 0.18 Micron Technology for RF Energy Harvest Application

Abstract: RF signal carries very low amount of energy and can be easily dissipated as heat loss. Threshold voltage and leakage current that are inherent in MOS transistors significantly affect the performance of an RF AC to DC converter. A device with bulk connected to its drain improves the threshold voltage and leakage current. This work designs the half-wave and full-wave AC to DC converters with devices' bulk connected to source and devices' bulk connected to drain. The designs used the native devices in TSMC 0.18 micron CMOS technology, and were simulated using transient analysis in different process corners and operating temperatures. In simulations, the RF signal was represented by a sinusoidal input of 900 MHz frequency and of 390 mV amplitude. The sizes of transistors and the number of stages, of each converter, that resulted to highest power efficiency were determined via circuit simulations. The optimal design was a four-stage half-wave AC to DC converter with devices' bulk connected to drain, which produced a DC output of 2.7 V with 37.42 % efficiency at 100 kilo ohm load.

A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations

Abstract: A cross-layer framework (spanning device and circuit levels) is presented for designing robust and energy-efficient SRAM cells, made of deeply-scaled FinFET devices. In particular, 7nm FinFET devices are designed and simulated by using Synopsys TCAD tool suite, Sentaurus. Next, 6T and 8T SRAM cells, which are composed of these devices, are designed and optimized. To enhance the cell stability and reduce leakage energy consumption, the dual (i.e., front and back) gate control feature of FinFETs is exploited. This is, however, done without requiring any external signal to drive the back gates of the FinFET devices. Subsequently, the effect of process variations on the aforesaid SRAMs is investigated and steps are presented to protect the cells against these variations. More precisely, the SRAM cells are first designed to minimize the expected energy consumption (per clock cycle) subject to the non-destructive read and successful write requirements under worst-case process corner conditions. These SRAM cells, which are overly pessimistic, are then refined by selectively adjusting some transistor sizes, which in turn reduces the expected energy consumption while ensuring that the parametric yield of the cells remains above some prespecified threshold. To do this efficiently, an analytical method for estimating the yield of SRAM cells under process variations is also presented and integrated in the refinement procedure. A dual-gate controlled 6T SRAM cell operating at 324mV (in the near-threshold supply regime) is finally presented as a high-yield and energy-efficient memory cell in the 7nm FinFET technology.

A 120 nW, Tunable, PVT Invariant Voltage Reference with 80 dB Supply Noise Rejection

Abstract: This work presents a process, voltage and temperature (PVT) invariant tunable voltage reference generator in 180 nm CMOS technology. Using weighted averaging of tuned PTAT and CTAT voltages at zero temperature coefficient point, the proposed design exhibits only ±0.28% variation in post-layout simulation across process corners over a temperature range of-25 degree C to 100 degree C. Maximum deviation (±3 sigma/mean) from the desired value of the reference voltage is ±2.1% in the untuned case, as obtained from 1000 Monte Carlo runs. Worst case temperature and power supply sensitivity of the tuned reference across process corners are 45 ppm/degree C with 1.8 V supply and 0.18%/V at 27 degree C, respectively. Power supply noise rejection (PSNR) for frequencies between 100 Hz and 100 MHz is > 80dB, with a maximum PSNR of 90dB near 1 kHz. With the use of sub threshold MOSFETs, the DC power consumed by the design is only 300 nW when operated at a nominal supply voltage of 1.8 V. The circuit works even with a supply voltage as low as 0.8 V, while consuming 120 nW DC power.

Automatic design of high-order SC filter circuits

Abstract: The manual design of Switched-Capacitor (SC) filters can be a strenuous process. This task becomes even more complex when the high gain amplifier is replaced by a low gain amplifier due to the loss of the virtual ground node, increasing the complexity of the filter's transfer function and requiring the compensation of the parasitic capacitances during the design phase. This paper proposes an automatic procedure for the design of high order SC filters using low gain amplifiers. The design methodology is based on a Genetic Algorithm (GA) using hybrid cost functions with varying goal specifications. The cost function first uses equations for the estimation of the filter's transfer function and, once the specifications are met, the filter is further optimized in order to increase its robustness to random variations. Afterwards, the gain and settling time of the amplifier is also estimated using equations and optimized against several process corners. The use of equation-based cost functions reduces the computation time, allowing the use of larger populations to cover the entire design space. Once all specifications are met, the GA uses transient electrical simulations of the circuit in the cost functions, resulting in the accurate determination of the filter's transfer function, and obtaining the final design solution within a reasonable amount of computation time.

Designing CMOS for Near-Threshold Minimum-Energy Operation and Extremely Wide V-F Scaling

Abstract: This work proposes a strategy for designing VLSI circuits to operate in an extremely wide Voltage-Frequency Scaling (VFS) range, from the supply voltage at which the minimum energy per operation (M EP) is achieved, up to the nominal voltage for the process. First the sizing methodology of two library cells using transistors with different threshold voltages: Regular-VT (RVT) and Low-VT (LVT) is described. Just five combinational cells: INV, NAND, NOR, OAI21, and AOI22 comprise the libraries plus two register cells, all with multiple strengths, for RVT ones. The sizing rule for the transistors of each cell is directly driven by requiring equal rise and fall times in order to attenuate variability effects at very low supply voltages. These cell libraries were characterized for typical, fast, and slow process corners, over temperature (−40°C, 25°C, and 125°C) variations, and for supply voltages varying from 200 mV up to 1.2 V with small supply steps. Circuit syntheses were performed for ten VLSI circuit benchmarks: notch filter, 8051 compatible core, and eight ISCAS benchmark circuits, considering all VDD operating points. We show that at the optimum MEP point (near-VT) an average reduction of 54.46% and 99.01% in energy is possible, when compared with deep sub-threshold and nominal supply voltages, respectively, at room temperature. The extremely wide VFS regime enables operating frequencies varying from hundreds of kHz up to MHz/GHz at −40°C and 25°C, and from MHz up to GHz at 125°C. The near-VT designs herein presented, when compared to related work, showed on average an energy reduction and performance gain of 24.1% and 152.68%, respectively, for the same circuit benchmarks. Comparison of near-VT operation at very low and high temperatures show advantages for a hotter CMOS operation for this regime.

A fully-differential OTA in 28 nm UTBB FDSOI CMOS for PGA applications

Abstract: This paper presents a fully-differential operational transconductance amplifier (OTA) designed in a 28 nm ultra-thin box and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. An overview of the features of the 28 nm UTBB FDSOI process which are relevant for the design of analog/mixed-signal circuits is provided. The OTA which features continuous-time CMFB circuits will be employed in the programmable gain amplifier (PGA) for a 9-bit, 1 kS/s SAR ADC. The reverse body bias (RBB) feature of the FDSOI process is used to enhance the DC gain by 6 dB. The OTA achieves rail-to-rail output swing and provides DC gain = 70 dB, unity-gain frequency = 4.3 MHz and phase margin = 68° while consuming 2.9 μW with a V dd = 1 V. A high linearity > 12 bits without the use of degeneration resistors and a settling time of 5.8 μs (11-bit accuracy) are obtained under nominal operating conditions. The OTA maintains satisfactory performance over all process corners and a temperature range of [−20°C +85°C].

A tunable multi-band/multi-standard receiver front-end supporting LTE

Abstract: Current wireless communication devices demand multi-band/multi-standard receiver that can access all the available services specifications. This work introduces a tunable receiver front-end for multi-band multi-standard applications. The receiver adopts a down-conversion quadrature band-pass FIR charge sampling mixer tuned via its controlling clocks. A time varying impedance matching network provides further selectivity. The architecture is simulated over three different frequencies spanning two octaves (2G, 1G and 500MHz) targeting LTE specifications. The proposed design is tested across process corners and post layout. Simulations result in Noise Figure of 7.5 to 9 dB, out-of-band IIP3 of −1.9 to −7 dBm, in-band IIP3 of −1.5 to −10 dBm and S11 <−10dB. The design is implemented using 65nm CMOS technology.

Design and implementation of 1 GHz Current Starved Voltage Controlled Oscillator (VCO) for PLL using 90nm CMOS technology

Abstract: In wireless communication system the phase locked loop plays important role, specially Voltage Controlled Oscillator. It is an electronic device which is used for the purpose of generating a signal. Applications range is very vast, which includes clock generation in various microprocessors to carrier synthesis in cellular telephones, requiring a large range of different oscillators/signal generation topologies and the performance parameters differs as the need changes. VCO can be designed and built using many circuit techniques. This paper presents one of the ways to design and implementation of CMOS voltage controlled oscillators (VCO) for pll. A VCO is an oscillator circuit, where the control voltage controls the oscillator output frequency. In this paper CSVCO is has been designed Cadence Design Suite using GPDK 90nm CMOS Technology with supply voltage 1.8v. Intern Virtuoso Analog Design Environment tool of Cadence have used to design and simulate schematic. Simulation results are calculated for all process corners, temperature (−40°C to +100°c).

A Linear Comparator-Based Fully Digital Delay Element

Abstract: A linear delay element is proposed in 0.18 µm CMOS technology with a power supply of 1.8V. The proposed delay element maintains linearity over a relatively large input voltage range of 1.2V and its delay range (sensitivity) can be tuned through a bias voltage. Its power dissipation is 50a#x03BC;W at a clock frequency of 1GHz and its robustness in different process corners has been shown through simulations. Additionally, a 6-bit 107MS/s Fully Digital ADC with 1.2 V input range has been implemented using the proposed delay element. The simplicity of design and functioning of the proposed delay element contributes to its improved power and energy consumption.

Semiconductor device and temperature control method of semiconductor device

Abstract: According to one embodiment, a semiconductor device includes: an integrated circuit that has a plurality of power consumption modes different in power consumption; a temperature detection circuit that detects temperature of the integrated circuit; a counter that measures time taken for temperature change in the integrated circuit; and a state machine that causes a state transition to take place in the integrated circuit based on the temperature detected by the temperature detection circuit and the time measured by the counter, wherein the integrated circuit selects the power consumption mode based on the state subjected to transition by the state machine.

Implementing enhanced bias configuration for cmos inverter based optical transimpedance amplifier

Abstract: A method and circuit are provided for implementing an enhanced bias configuration for CMOS inverter based optical Transimpedance Amplifiers (TIAs). An operational amplifier is provided in a feedback configuration that forces an input of the CMOS inverter to a set voltage level by regulation of the inverter power supply. A photo-detector sees a more stable bias voltage, and the responsivity of the photo-detector is more robust and the TIA has improved performance across process corners.

A high efficiency rectifier for inductively power transfer application

Abstract: This paper presents a high efficiency rectifier for inductively power transfer application. The efficiency of the rectifier is optimized by utilizing unbalanced biasing technique in the proposed wide swing cascode comparator controlled switch to suppress the reverse leakage current. The design is implemented in standard CMOS 0.18um AMS process. The targeted application is for telemetry, for use in the ISM band between 125 kHz and 134 kHz. The proposed rectifier achieves a peak power conversion efficiency (PCE) of 94.9% in the frequency range of 125kHz – 2MHz with an AC amplitude ranges from 1.2 V to 2.5V under maximum load current condition. It can source a maximum load current of 55mA and operates well under all process corners conditions.

A process corner detection methodology for resilience towards process variations using adaptive body bias

Abstract: The nanometre scale technology is fundamentally different from its predecessors as they are exposed to a wide variety of new effects that are induced on the transistor chips. One of the reliability degradation effects is process variation which plays a relevant mantle as it leads to performance degradation. The work presented in this paper explains an all process corner (SS, SF, FS & FF) detection scheme for providing tolerance towards process variations using Adaptive Body Bias (ABB). In this scheme, an on-chip monitor detects the process corner at which the circuit is operating and a corresponding adaptive body bias is generated by the body biasing circuit which is supplied to the transistors. The simulations are performed taking V BB as 0, i.e., No Body Bias (NBB) and by supplying a finite adaptive body bias (ABB) voltage to the transistors on the chip and their corresponding mean and variance have been calculated using Monte Carlo histograms. Simulations have been performed on a critical path which has been extracted from a microprocessor at 32 nm predictive technology model using HSPICE. Monte Carlo simulations of 10,000 runs demonstrate that the proposed approach provides tolerance to process variations under all process corners. The proposed approach has shown to reduce the impact of process variations on frequency, dynamic power & leakage power and a reduction in the values of relative standard deviation (σ/μ) conforms to our circuit approach.