Showing papers on "Process corners published in 2018"

A PUF scheme using competing oxide rupture with bit error rate approaching zero

Abstract: Security is critical to today's interconnected world, and hardware protection is equally important as security at the network and system levels. Silicon physically unclonable functions (PUFs) are increasingly used as a hardware root of trust and an entropy source for cryptography applications. In those applications, the reliability of PUF output is key to a successful implementation. Both weak and strong PUFs obtain output by amplifying analog signals from physical properties on IC blocks (e.g. propagation delay, ring oscillator, time-controlled oxide breakdown [1] or threshold voltage of SRAM transistors [2,3,4]). These physical measurements are by nature sensitive to environmental conditions, such as temperature, operating voltage, thermal/interface noise of transistors, process corners and aging. As a result, it is difficult to obtain a stable PUF output without taking additional stabilization and error-correction techniques, e.g. temporal majority voting (TMV), pre-burning on PUF bits for end-of-life (EOL) prediction and reliability screening, masking algorithms, as well as leveraging parity bits for an Error-Correcting-Code (ECC) [3,4]. This paper presents a PUF architecture fabricated in 55nm ultra-low-power (ULP) CMOS and 55nm embedded Flash. The scheme is able to produce reliable and uniformly random PUF output without the need for complex error correction or error bit testing.

A new grounded memristor emulator based on MOSFET-C

Abstract: In this paper, memristor emulator circuit consisting of only seven MOS transistors and one grounded capacitor is presented. Memristors exhibit nonlinear voltage-current relationship and many previous emulator circuits have multiplier circuit to provide the nonlinear characteristic of the memristor. But there is no any multiplier circuit block in the proposed circuit so the proposed memristor circuit occupies low chip area. The memristor circuit is laid by using Cadence Environment with TSMC 0.18 µm process parameters and its layout dimensions are only 12 µm × 38 µm excluding the area of the capacitor. The post-layout simulation results for memristor are given to demonstrate the performance of the presented memristor emulator in different operating frequencies, process corner, and radical temperature changes. All post-layout simulations agree well with theoretical analyses. Besides the VLSI implementation of the memristor, the proposed circuit is built on the breadboard using discrete circuit elements.

The Fabrication and MOSFET-Only Circuit Implementation of Semiconductor Memristor

Abstract: In this paper, a ZnO-based semiconductor thin film memristor (300 nm in thickness) device is fabricated using metallic top and bottom electrodes by direct-current reactive magnetron sputter. The memristive characteristics of the device were completed by time-dependent current–voltage ( ${I}$ – ${V}$ - ${t}$ ) measurements, and the typical pinched hysteresis ${I}$ – ${V}$ loops of the memristor were observed. This paper is continued with the designing memristor emulator circuit, which has only four MOS transistors. The proposed circuit is suitable both for emulating the fabricated memristor and for using general memristor-based applications. Any circuit blocks such as a multiplier or active element are not used in the circuit to obtain memristive characteristics. All results of the proposed memristor emulator circuit are compatible with general characteristics of the fabricated semiconductor device. The MOSFET-based proposed memristor emulator circuit is laid out in the Analog Design Environment of Cadence Software using 180-nm TSMC CMOS process parameters and its layout area is 366 $\mu \text{m}^{\textsf {2}}$ . So as to show its performance, the dependences of the operating frequency and process corner as well as effects of radical temperature changes have been investigated in the simulation results section.

Compact Analytical Model to Extract Write Static Noise Margin (WSNM) for SRAM Cell at 45-nm and 65-nm Nodes

Abstract: The operation of static random access memory (SRAM) in the subthreshold region reduces both leakage power and access energy. Subthreshold operation is one of the proficient techniques to accomplish low-power and high performance system on chip. But the challenge, in subthreshold SRAM design, is the SRAM stability. The sensitivity to process variations increases with technology scaling resulting in reduced stability. In this paper, SRAM write stability is analyzed in the subthreshold region. The semi-analytical model of write static noise margin (WSNM) for 6T SRAM (subthreshold region) has been given in this paper. The results obtained from the analytical model are verified through simulations in Cadence using GPDK 45-nm, UMC 65-nm, and UMC 130-nm technology files. The model is based on the subthreshold current equations of the transistor. Further, the write stability of the SRAM is analyzed with the varying supply voltage and the sizing ratios. The process corner analyses is also accomplished to verify the write stability of the SRAM cell using the model at the worst process corners. To the best of the author’s knowledge, this is the first model to analyze the WSNM based on the traditional butterfly static noise margin approach. It has been observed that the model is valid for all of the technology nodes, i.e., at 45 nm, 65 nm, as well as 130 nm. Also the model holds well for 8T and 10T SRAM configurations in addition to 6T SRAM cell.

Low power dynamic circuit for power efficient bit lines

Abstract: In this paper, a low power dynamic circuit is presented to reduce the power consumption of bit lines in multi-port memories. Using the proposed circuit, the voltage swing of the pull-down network is lowered to reduce the power consumption of wide fan-in gates employed in memory’s bit lines. Wide fan-in OR gates are designed and simulated using the proposed dynamic circuit in 90 nm CMOS technology. Simulation results show at least 40% reduction of power consumption and 1.2X noise immunity improvement compared to the conventional dynamic circuits at the same delay. Exploiting the proposed dynamic circuit, wide fan-in multiplexers are also designed. The multiplexers are simulated using a 90 nm CMOS model in all process corners. The results show 41% power reduction and 27% speed improvement for the proposed 128-input multiplexer in comparison with the conventional multiplexer at the same noise immunity.

Schmitt trigger-based single-ended 7T SRAM cell for Internet of Things (IoT) applications

Abstract: The Internet of Things is an emerging application area which is going to become one of the leading electronic hubs in the semiconductor industry. The IoT systems require battery-enabled energy-efficient memory circuits to operate at ultra-low voltage (ULV). In this paper, a novel Schmitt trigger-based, single-ended 7-Transistor (7T) Static Random Access Memory (SRAM) cell which uses dynamic body bias technique for IoT applications is presented. The proposed 7T SRAM cell is designed using standard 45nm Complementary Metal Oxide Semiconductor technology at an ULV of 0.3V. The post-layout simulation results have shown more than 22% improvements in the Read Static Noise Margin and more than 44% write, 63% read energy savings in comparison with the conventional 6T cell, 7T, single-ended 8T, and Schmitt trigger 11T cell designs. The proposed design is also found to be stable at different process corners and supply voltages. A new quality metric SNM per unit Area to Energy Ratio which evaluates the overall performance of the SRAM cell design is calculated and is found to be highest for the proposed design.

Process Invariant Biasing of Ring Amplifiers Using Deadzone Regulation Circuit

Abstract: In this paper, process invariant biasing is proposed for robust operation of ring amplifiers. The ring amplifier is an efficient solution for high accuracy amplification in sub-micron CMOS process. A traditional ring amplifier structure requires an external control voltage, defined as the deadzone voltage, to set the optimum quiescent current at the output stage. Other structures of ring amplifiers use on-chip resistors or current starved inverters to set the deadzone voltage. Since the deadzone voltage is a function of the threshold voltage of transistors in the output stage inverter, ring amplifiers are susceptible to process variations. In this paper, a deadzone regulation circuit is proposed that utilizes a constant current source and a negative feedback loop to regulate the quiescent current of the output stage inverter across process corners. Transistor level simulations are used to validate the operation of the proposed deadzone regulation technique across FF, TT and SS corners in a 65nm CMOS process. The design example uses a current starved inverter based ring amplifier in a switched capacitor amplifier to achieve a closed loop gain of 4 with a settling accuracy of ≤ 0.05% and operated at a sampling rate of 125MHz.

A State-of-the-Art Current Mirror-Based Reliable Wide Fan-in FinFET Domino OR Gate Design

Abstract: With continued scaling of VLSI circuits, reliability has emerged out as one of the major circuit design challenges. Systematic die-to-die, random on-die as well as temperature and supply voltage variations are major sources of performance degradation which leads to unreliable circuits. Further, with reduced short channel effects at highly scaled nodes, the FinFET has recently been emerged as a suitable replacement of CMOS in the VLSI industry. Wide fan-in FinFET domino logic OR gate is one such circuit, which serves as an integral part of register file in a high-speed FinFET microprocessor. This circuit inherently suffers from low noise immunity which get worsens with circuit parameter variations due to process and temperature variations. At highly scaled technology nodes, it has been studied that the effects of on-die random process variation surpass the effects of systematic variations. Furthermore, at deep sub-nanometer scale the effect of process variation on device parameters is higher in FinFET as compared to CMOS. In this research work a reliable current mirror-based wide fan-in FinFET domino OR gate is proposed for temperature, random on-die and systematic die-to-die process variation tolerance. Simulation results at 32 nm FinFET process show that the proposed design is capable of maintaining high noise immunity (Unity Noise Gain of nearly 0.4 V) at all process corners and a constant performance (with reduced delay by 30% as compared to conventional design) in the presence of systematic as well as random process and temperature variations.

Automatic Selection of Process Corner Simulations for Faster Design Verification

Abstract: Integrated circuit designs are verified in simulation over a set of process corners, which are combinations of expected transistor properties, power supply voltages, and die temperatures. The simulation time per corner can be long and semiconductor processes can have more than 1000 corners. Simulation is thus a serious bottleneck in design verification. We propose an algorithm that selects the smallest number of process corner simulations that are required to estimate minimum and/or maximum values of the output functions that model circuit behavior. Using our best corner selection algorithm, the required number of process corner simulations is reduced by an average of 79% (a speed-up of 4.71) with respect to a set of 46 output functions from nine industrial benchmark circuits.

Performance Analysis in Digital Circuits for Process Corner Variations, Slew-Rate and Load Capacitance

Abstract: The aggressive scaling of CMOS technology has inevitably led to vastly increased power dissipation, process variability and reliability degradation, posing tremendous challenges to robust circuit design. To continue the success of integrated circuits, advanced design research must start in parallel with or even ahead of technology development. In this paper, an attempt is made to analyze various circuits’ delay and power performance by introducing certain level of variation to important process parameters like threshold voltage (Vth), mobility of carriers (μ0), oxide thickness (tox) and doping concentration (nsd). Basic Monte Carlo simulation is carried out on these circuits to ascertain the stability in performances. A 16 × 1 multiplexer is considered for detailed analysis. SPICE characterization is done for three different input slew rates (0.1, 0.5 and 1 ns) against four different output load drive strengths (1×, 2×, 3× and 4× output capacitive load). From the obtained results, output slew rates and average power results are observed and discussed.

Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications

Abstract: IoT edge devices require ultra-low leakage for lowly duty-cycled applications. The prior designs only show the all-N-type ripple carry adder (All-N-RCA) outperforming the static RCA design based on simulation results. To verify the feasibility and to increase the confidence level of applying dynamic circuit to the near- Vt SoC design, the design vehicle must be at least a pipelined design. We then propose the useful DSP kernel, the COordinate Rotation DIgital Computer (CORDIC) to be the test vehicle in this work. The core circuits of CORDIC ‘logarithmic shifter’ and ‘adder’ are replaced by dynamic circuit to build up proposed dynamic CORDIC. The static CORDIC and dynamic CORDIC are evaluated according to pre-layout simulation results in 28 nm CMOS technology. For an IoT application with a 0.02% and 0.2% duty cycle, the proposed dynamic CORDIC can achieves a 41% and 30% energy reduction compared to the static CORDIC at the typical process corner.

EMI-Related Common-Mode (CM) Noise Analysis and Prediction of High-Speed Source-Series Terminated (SST) I/O Driver in System-on-Package (SOP)

Abstract: This brief presents, for the first time, a comprehensive analysis and prediction of electromagnetic interference-related common-mode (CM) noise for a 20-Gb/s source-series terminated I/O driver in a 65-nm CMOS process. The novel methodology is proposed to systematically analyze and predict the CM noise of an output driver from various dependent parameters, including CMOS process corners, input signal, power supply, and passive interconnections. Analysis reveals that the nonlinear active circuit predominantly produces an asymmetric rise and fall time of the output signal and is an intrinsic source responsible for generating the CM noise. For the SST driver, as the result of the push–pull nMOS–pMOS configuration, CM noise level variations are aggravated under process corners. The post-layout simulation results indicate that the critical step in controlling the CM noise is at the source, rather than improving the matching of passive interconnections. The presented methodology can also be applied to other serializer/deserializer I/O drivers.

A Novel Multiple Membership Function Generator for Fuzzy Logic Systems

Abstract: This paper presents a new multiple membership function generator which is capable of forming Gaussian, trapezoidal, triangular, S-shaped, and Z-shaped membership functions. To the best of authors' knowledge, a single circuit that can concurrently generate Gaussian, trapezoidal, and triangular membership functions has not been reported in the literature yet. Proposed circuit is compatible with many fuzzy logic systems requiring different types of membership functions. The circuit is designed using a commercial 0.18 μ m CMOS technology and consumes a total power of 180μ W. The shapes of each membership function can be modified by properly chosen values of input and reference voltages. Functionality of all membership functions is validated across process corners with additional Monte Carlo analysis where temperature variations are considered, as well.

Characterization of a 0.35-Micron-Based Analog MPPT IC at Various Process Corners

Abstract: An analogue maximum power point tracking (MPPT) controller integrated circuit (IC) based on ripple correlation control was modified for low voltage applications in this study to harvest the maximum power from the photovoltaic array or solar panel under partial shading and changes in temperature. The IC was implemented in TSMC 0.35um 2P4M 5V mixed-signal CMOS technology. It was simulated at various process corners namely: typical-typical (TT); slow-slow (SS); fast-fast (FF); slow-fast (SF); and fast-slow (FS). The simulation results showed that at a 400 W/m2 solar irradiance and 25 degrees Celsius temperature, the tracking efficiencies are 99.18%, 98.55%, 98.89%, 98.96%, and 98.90% at different process corners, TT, FF, FS, SF, and SS, respectively.

Projected Tolerances of Carbon Nanotube Current-Mode Logic to Process Variability

Abstract: Radio frequency (RF) analog applications present an interesting opportunity for carbon nanotube (CNT)-based electronics. Extrinsic peak operating frequencies of up to 40 GHz for CNT field-effect transistors manufactured on wafer scale employing very moderate dimensions have been already demonstrated. However, as in any emergent technology, variability of the fabricated devices is significant. Therefore, predictions about the behavior of benchmark circuits at the process corners are required to further stimulate complex RF design and fabrication. We report here on the projected tolerance of a current-mode logic (CML) buffer/inverter designed for 2.4 GHz (5 Gb/s), 1.8-V supply voltage, 1.8-mA tail current, and a 600-mV voltage swing. The single CML stage is very robust against variations in CNT density but vulnerable to source-drain shorts introduced by metallic tubes in the channel. A corresponding five-stage CML ring oscillator shows considerably reduced output voltage swing beyond two percent metallic tube fraction indicating the importance of metallic tube reduction by technology dependent strategies like presorting, post-elimination, or type-selective growth.

A Disturb Free Read Port 8T SRAM Bitcell Circuit Design with Virtual Ground Scheme

Abstract: This paper presents new 8T SRAM design that avoids the stability and reliability issues of the conventional 6T and other existing SRAM cells. The proposed 8T SRAM is as good as the 10T design without the overheads of the 10T cell. In the proposed design, the virtual ground technique weakens the positive feedback and improves the writeability of the cell. The read operation does not require any precharging circuit leading to reduced area overheads for the SRAM memory system. The design isolates the storage node from the read path, which improves the read stability. For reliability study, we have investigated the static noise margin (SNM) of the proposed 8T SRAM and compared with the conventional designs at different process corners. The delay of the proposed bitcell is reduced to 69.67% during write and 52.87% during the read compared to conventional 6T bitcell. In addition to this, leakage currents of the proposed 8T bitcell reduced to 4.24%, 9.5% and 18.65% in the hold, read and write operations in contrast to conventional 6T bitcell. We have also analyzed the impact of the process and parametric variations in the proposed 8T SRAM using Monte Carlo simulations.

Design of Robust Ultra-Low Power CMOS Voltage Controlled Ring Oscillator with Enhanced Performance

Abstract: Sub threshold circuits have proven their ability to satisfy the demand of ultra low power consumption of today's battery operated applications. However, the elevated variability and degraded performance issues of sub threshold circuits need to be addressed. This paper focuses on dual knobs of variability and performance of sub threshold CMOS VCO and proposes an ultra low power CMOS voltage controlled ring oscillator with enhanced performance and reduced variability. The proposed DTCSVCO configuration exhibits better performance and slew as compared to conventional CSVCO by almost 37% and 10.87% respectively. Width optimization further improves the performance of proposed DTCSVCO by almost 49% at the cost of increase in PDP of 32%. Process and temperature variability is also investigated and the results illustrates that the proposed DTCSVCO exhibits better robustness compared to conventional CSVCO. The simulation results at different process corner over a wide range of temperature are consistent.

N-Curve Analysis of Low power SRAM Cell

Abstract: In this paper, a low power SRAM cell is proposed, whose leakage power is almost negligible compared to that of conventional 6T SRAM cell. All the stability parameters like static voltage noise margin(SVNM), static current noise margin(SINM), write trip voltage (WTV) and write trip current (WTI) are calculated using N-curve analysis. A better write stability is achieved for the proposed cell than 6T SRAM cell with a slight reduction in the read stability. The N-curves are plotted under different process corners and different temperatures. The standby power of the 6T SRAM cell and proposed SRAM cell is 6.22nW and 4.23uW respectively. Therefore, for low standby power applications the proposed cell is more suitable. Cadence tools are used for simulation of SRAM cells with gpdk 45-nm technology.

Process Variation-Aware Datapath Employing Dual Mode Logic

Abstract: Dual Mode Logic (DML), which was recently introduced by our group, offers the possibility to operate digital gates either in the static mode to save energy, or in the dynamic mode to increase speed albeit with a higher delay or energy consumption, respectively. We showed that on-the-fly switching of critical paths between the static and dynamic modes enabled system self-adaptation to computational needs achieving both high speed and low energy consumption. In this paper, for the first time we show that the mixed mode operation of a DML based datapath can efficiently reduce design sensitivity to process variations at near threshold voltages. Specifically, the number of gates operating in the dynamic mode (when the datapath is switched to the high-performance mode) is selected as a function of the process corner. The number of dynamically operated gates can be adjusted during the post-silicon phase or at run-time with an architectural level solution. In a basic proof of concept, simulations of a chain of 20 NAND/NOR gates demonstrated that process variations were successfully alleviated by utilizing an optimal configuration of the chain. The DML design can meet CMOS TT performance requirements in the SS corner and save energy by 18% in the FF corner. A 64-bit ripple carry adder (RCA) confirmed the advantages of DML over CMOS for different optimization points.

A Temperature Variation Tolerant CMOS-Only Voltage Reference for RFID Applications

Abstract: In this paper a reference voltage circuit is presented for outdoor RFID applications. The circuit consists of a Dickson charge pump and a series of stacked diode connected CMOS devices. With this configuration we have introduced a new approach to produce a 1.515V reference voltage from a Dickson charge pump which shows robust behavior against temperature variation. Taking advantage of a harvested RFID signal rendered the circuit suitable for a wide range of applications in which energy and area constraints are of great concern. The circuit has been designed with conventional CMOS devices using a commercial 40nm technology and simulated with cadence. The proposed circuit consumes 235nW power with 88 PPM/○C temperature coefficient in temperature range of −10°C to 125°C. The total active area of the circuit is 0.00036mm2. The circuit shows +10% −12% variation from the nominal value due to process corner analysis and its PSRR(dB) is −47©915MHz.

PVT compensated high selectivity low-power balun LNA for MedRadio communication

Abstract: A single-to-differential low-noise amplifier (LNA) is proposed for low-power medical devices in the frequency band of 401-406 MHz. The proposed LNA avoids the use of surface acoustic wave (SAW) filter and additional balun in RF receiver front-end. The LNA comprises inductive degeneration common source (IDCS) technique (stage I) and a cascaded common source circuit (stage II). The stage-II is stacked on top of stage-I. The proposed balun LNA incorporates single to differential (SD) conversion for minimum gain and phase error. A compensation bias circuit is proposed to minimise variations in parameters of LNA against process corners, supply voltage and temperature (PVT). An upsurge balun LNA is designed in UMC 0.18-μm CMOS technology, the DC power consumption is 290 μW under a supply voltage of 1 V and the minimum noise figure is 3 dB. The die area of LNA including buffers and bias circuit is 850 μm × 978 μm. The worst-case post layout simulation results show a gain and phase error of 0.8 dB and 10°. The percentage variation of gain and NF against PVT is reduced by 55 and 48%. Furthermore, the balun LNA has out of band rejection at the roll-off rate better than 70 dB/dec.

Over Temperature Protection Circuits for Integrated Power Converters

Abstract: Integrated power converters suffer from overheating when they operate under extreme conditions To prevent destructive breakdown an over-temperature protection (OTP) circuit is usually designed along with circuits, which restricts the chip temperature within a threshold level From a design standpoint, OTP output should vary within a limit range throughout the whole process corners in order to support the chip's reliability The paper presents an OTP circuit design to limit fluctuations in triggering and reset points by reducing the comparator errors Simulated results revealed the designed OTP circuit can reach less than 10 % variation over 300 different corners

Design and Implementation of High Speed Sense Amplifier for SRAM

Abstract: The Sense amplifier’s sense delay is one important parameter to measure the speed of SRAM memory cell. The sense delay depends on the amplifier reaction time. This delay parameter is more vulnerable to device variations, temperature and supply voltage variations. A latch type voltage controlled sense amplifier considered among all the offered current and voltage sense amplifier types for data sensing from the SRAM cell. The modified conventional latch type voltage controlled coupling capacitor based sense amplifier is implemented to improve the performance of the memory cell. The proposed circuit scheme will provide the reasonable negative voltage at the sense amplifier virtual ground, then the driving capability of the pull down (NMOS) transistors is increased, hence it made the sense amplifier faster. The conventional sense amplifier is compared with proposed coupling capacitor sense amplifier. From the experimental results, it is observed that coupling capacitor based sense amplifier circuit scheme will decrease the sense amplifier reaction time and access the data fast. The result shows, the proposed scheme provides the improvement of sense delay reduction of 198ps at SS/-40o C/1.2v and 18ps at FF/127o C/1.2v process corners at the cost of power consumption.

Design of a temperature-insensitive digitally-controlled oscillator for on-chip reference clock

Abstract: This paper presents a 0.4V temperature-insensitive digitally-controlled ring oscillator (DCO) for on-chip reference clock circuit. Based on a modified bootstrapped ring oscillator (BTRO), temperature variation can be further decreased without calibration, where BTRO is operated at near-threshold voltage. A binary-weighted tree-controlled resistor network (BWTRN) is performed to achieve an 8bit high-linearity DCO with BTRO. The proposed DCO is fabricated in TSMC 90 nm CMOS process with a core area of 0.013 mm2. The simulation results in typical corner demonstrate that the DCO oscillates max/min frequency of 105.6MHz/60.7MHz at 0.4 V V dd and consumes 8.77μW/4.44μW. The maximum temperature variation of the single code is 329 ppm, and its maximum DNL variation is 0.67 LSB. Even for all process corners, the maximum temperature variation among all control codes is 8%.