Showing papers on "Process corners published in 2020"

A Self-Tuning IoT Processor Using Leakage-Ratio Measurement for Energy-Optimal Operation

Abstract: Energy-optimal operation is one of the key requirements of the Internet-of-Things (IoT) applications to increase battery life. In this article, using a combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB), the energy-optimal operation is achieved with a given fixed operating frequency determined by application demands. Based on the observation that the ratio of leakage power to dynamic power can be an accurate indicator for the optimal operating point, the proposed method dynamically tracks the minimum energy operating points by adjusting supply voltage and body bias with very low hardware and power overhead. A custom dc–dc converter for supply voltage regulation and charge pumps for body bias generation were implemented with the proposed method in a Cortex-M0 processor. Since SRAM is included in the same energy optimization loop as the processor, a custom SRAM was designed to match the processor speed. The design is fabricated in an Mie Fujitsu Semiconductor (MIFS) 55-nm deeply depleted channel (DDC) CMOS and the proposed approach achieves energy consumption within 4.6% of optimal at 1 MHz across five process corners and temperatures from −20 °C to 125 °C. The fabricated processor achieves 6.4 pJ/cycle at 0.55-V and 500-kHz clock frequency.

Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance

Abstract: Double-node upsets induced by the charge sharing effects are emerging as a major reliability issue in nanometer latch design. Although the existing robust latches can provide a good tolerance for double-node upsets, the implementation of these hardened latches incurs in considerable hardware penalties in terms of delay, area, and power, because they rely on traditional hardening techniques such as space redundancy. In this paper, a novel low-complexity (with respect to hardware redundancy in terms of area, delay, and power) radiation hardened (RH) latch is proposed; this latch is based on the dual interlocked storage cell (DICE). Based on the radiation upset mechanism, in particular the upset polarity of the transient pulse, the proposed RH latch can effectively reduce the number of protected nodes (sensitive nodes), as well as the number of transistors, thus reducing circuit overhead. At the same, a single node upset in any sensitive node and a double-node upset in any sensitive node pair can be recovered, because at least two stable nodes can retain the values even when a double-node upset occurs. The results are based on mapping designs to TSMC 65 nm commercial CMOS process design kit (PDK) and demonstrate that the proposed RH latch incurs in significant reductions in terms of propagation delay, circuit area, and power-delay-area product (PDAP), compared with existing hardened latches. The tolerance functionality of the proposed latch is successfully validated by fault injection. In addition, the impact of variations and process corners is assessed using Monte Carlo (MC) simulation. The simulation results confirm that the proposed latch can also tolerate all upsets, even under extreme values of process variations.

Design and analysis of ultra high-speed low-power double tail dynamic comparator using charge sharing scheme

Abstract: In this paper, an ultra high speed dynamic comparator is presented. The PMOS pass transistors are used in the latch and pre-amplifier stage of the comparator. At the regeneration phase, the latch is activated faster with sufficient preamplification gain and very less power consumption. Meanwhile, a cross-coupled set up of NMOS transistors in latch stage enhances the gain and speed. Unlike the previous reported comparator, the proposed dynamic circuit avoids the extra power consumption as well as delay, and establishes the optimum offset and kickback noise. The benefits in delay and power are verified with the help of analytical expressions, meticulous Monte Carlo simulations and process corner analysis in CADENCE SPECTRE at 90 nm CMOS technology. The simulation results validate that the proposed structure provides the about 2.5 times better speed and minimizes the power consumption by 3 times in comparison to hybrid double tail dynamic comparator with only 0.348 fJ/conv. energy per conversion. Moreover, it provides 2.44 mV offset with optimum kickback noise and area.

Subthreshold biased enhanced bulk-driven double recycling current mirror OTA

Abstract: This paper presents a single-stage bulk-driven double recycling low-voltage low-power operational transconductance amplifier (OTA) operating in subthreshold region. The proposed OTA utilizes double recycling topology and provides enough open loop voltage gain, slew rate, and unity gain frequency (UGF). The flipped voltage follower-based adaptively biased input differential pair working in class AB mode has ensured dynamic current boosting and increased slew rate. Further, the proposed OTA has utilized partial positive feedback to mitigate some of the performance reduction caused by the bulk-driven topology. The simulation results of the proposed OTA have ensured open loop gain of 79.5 dB, UGF of 37.1 kHz, and phase margin of 64°. It operates with dual power supply of ± 0.25 V and consumes low power of 60 nW. These performance parameters validate its usefulness for LV, LP and low-frequency applications. The process, voltage, and temperature variation effects on low-frequency voltage gain, UGF, and phase margin of the proposed OTA has also been investigated with process corner simulations. The proposed OTA is designed and simulated in UMC 180 nm standard n-tub bulk CMOS process technology utilizing Tanner EDA tools.

A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier

Abstract: This paper presents a process, voltage, and temperature (PVT)-insensitive dynamic amplifier (DA) with gain enhancement for a pipelined successive approximation register (SAR) analog-to-digital converter (ADC). The gain shift due to temperature and process variation is attenuated through the counteraction of input transconductance and delay-based integration time. Furthermore, based on charge conservation, a gain-folding technique is proposed to improve the gain limit of conventional DA, tripling the gain amplitude. The proposed DA is incorporated in a design of a 12-bit 100 MS/s SAR ADC. In 65 nm CMOS process, at 100 MS/s, the prototype ADC achieves an SNDR (signal-to-noise plus distortion ratio) of 65.7 dB and a Walden FoM of 12.06 fJ/conversion-step for a near-Nyquist input. The power dissipation is less than 1.9 mW. No more than 1.65 dB SNDR variations are obtained for supply voltage varying from 1.15 to 1.25 V and temperature varying from −20 °C to 125 °C with various process corners, respectively.

Statistical Stability Characterization of Schmitt Trigger Based 10-T SRAM Cell Design

Abstract: In this paper, stability analysis of conventional 6-T SRAM cell and Schmitt trigger (ST) based 10-T SRAM cell with optimized sizing parameters has been performed and compared. The read stability, write ability, delay and dissipated power have been investigated. By using N-curve methodology a significant improvement of 4.49%, 5.13% and 28.65% in SVNM, SINM and WTI respectively was observed for Schmitt trigger (ST) based 10-T SRAM cell as compared to optimized 6T SRAM cell. Furthermore, the effects of supply voltage and temperature on conventional 6T SRAM stability in read and write operational mode have also been examined. Furthermore, both read delay and read current were investigated for ST based 10-T SRAM cell and found in desirable limits. It is also interesting to note that read delay is improved by 66%. Monte-Carlo simulation of the ST based 10-T SRAM cell circuit is carried out in order to find the deviation for power and the read current. The read current of the 10T topology is found to be 29.97μA with standard deviation of 4.55μA. Mean dynamic power for all process corners is also calculated by monte-carlo simulation of 4000 point each and deviation from the mean power was obtained. For simulation process 90nm technology node at 1V power supply was used on cadence virtuoso tool.

A Sub-1-V 100-mA OCL-LDO Regulator With Process-Temperature-Aware Design for Transient Sustainability

Abstract: In this article, an output-capacitorless low-dropout (OCL-LDO) regulator that features low-power, small-transient-spike, and process-temperature (PT)-aware design for transient sustainability is presented. The circuit architecture is based on the improved PT-aware current source for keeping stable bandwidth and the proposed PT-aware transistor biasing network in conjunction of dual fast local feedback (DFLF) loops in a single power transistor stage to yield both enhanced and sustained transient metrics under a sub-1-V supply. Fabricated in 40-nm CMOS technology, the regulator can deliver a full-load current of 100 mA at a 100-pF load under a 0.75-V supply. From the measured results of 12 samples, it consumes an average quiescent power of 19.5 $\mu \text{W}$ and quiescent current of 26 $\mu \text{A}$ . It displays an average settling time of 414 ns for a full-load current of 100 mA at room temperature. The average load transient voltage spike is 23.9 mV and small when compared to the reported works at a similar level of load current. Finally, the process corner simulations at different temperatures together with the 12 measured samples at temperature corners have validated the sustainability of transient metrics.

Efficient Supply Modulator for Wide-Band Envelope Elimination and Restoration Power Amplifiers

Abstract: A fast transient response supply modulator has been realized and verified in envelope elimination and restoration (EER) power amplifier. The analysis and detailed design of the proposed architecture is presented. Simulation results, in 130-nm CMOS technology, show that the proposed supply modulator achieves better linearity and efficiency compared to the conventional hybrid mode supply modulators or hybrid EER when signal frequency increases. Adjacent channel leakage ratio requirements are met for an LTE signal with 5 MHz, 10 MHz, and 20 MHz BW with error vector magnitude less than 3% and efficiency of 79%, 73%, and 67%, respectively at an output power of 0.45 W. Post-layout simulations are performed across different process corners and the effects of real off-chip components and routes are taken into consideration to verify the robustness of the proposed solution.

Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design

Abstract: Optimization algorithms have been successfully applied to the automatic design of analog integrated circuits. However, many of the existing solutions rely on expensive circuit simulations or use fully customized surrogate models for each particular circuit and technology. Therefore, the development of an easily adaptable low-cost and efficient tool that guarantees resiliency to variations of the resulting design, remains an open research area. In this work, we propose a computationally low-cost surrogate model for multi-objective optimization-based automated analog integrated circuit (IC) design. The surrogate has three main components: a set of Gaussian process regression models of the technology’s parameters, a physics-based model of the MOSFET device, and a set of equations of the performance metrics of the circuit under design. The surrogate model is inserted into two different state-of-the-art optimization algorithms to prove its flexibility. The efficacy of our surrogate is demonstrated through simulation validation across process corners in three different CMOS technologies, using three representative circuit building-blocks that are commonly encountered in mainstream analog/RF ICs. The proposed surrogate is 69 X to 470 X faster at evaluation compared with circuit simulations.

A 4-MHz Digitally Controlled Voltage-Mode Buck Converter With Embedded Transient Improvement Using Delay Line Control Techniques

Abstract: In this article, a digitally controlled voltage-mode buck converter with embedded transient improvement using delay line-based control techniques is presented. Two voltage-controlled delay lines (VCDL’s) are used to convert the difference between the feedback and reference voltages to a delay time difference. The delay difference is then fed to the multiple-outputs bang-bang phase detector (MOBBPD), which converts the input delay difference to multiple-bits digital codes in a simple nonlinear way. The MOBBPD scheme leads to high resolution for small output ripple and improved response when large load transient happens in a low-cost way. A digital loop filter (DLF) accumulates the MOBBPD output codes to control the duty cycle through a novel digital pulse width modulator (DPWM) to regulate the output voltage. By designing the coefficients of the DLF, a type-II compensator can be achieved through the integral and proportional paths to make the loop stable. The proposed DPWM, which consists of a divide-by-8 frequency divider, two delay lines and a few simple digital logics, achieves a wide tunable range of duty cycle under various process corners and supply voltages. A proof-of-concept design of the proposed buck converter was fabricated in a standard $0.18~\mu \text{m}$ CMOS technology. The measured results show that it achieves a very wide output voltage range from 0.1 V to 3.5 V for a input supply range from 2.4 V to 3.6 V. With a 400 mA step in the load current, the overshoot/undershoot is less than 87 mV and the 1% settling time is less than $16~\mu \text{s}$ . The peak efficiency is 95.2% with 250 mA load current at 2.4 V output voltage with 3.3 V input voltage.

A Static Contention-Free Differential Flip-Flop in 28nm for Low-Voltage, Low-Power Applications

Abstract: A Static Contention-free Differential Flip-Flop (SCDFF) is presented in 28nm CMOS for low voltage and low power applications. The SCDFF offers fully static and contention-free operation without redundant internal clock toggling with footed differential latches, while keeping same area with conventional transmission-gate flip-flop (TGFF). The fully static and contention-free operation allows high variation tolerance at low supply voltage regime, achieving wide-range voltage scalability (1V to 0.3V). Measurement results with test chip fabricated in 28nm CMOS technology show that power consumption is reduced by 64%/56% with 0%110% activity at IV, compared to the TGFF. All 100 dies from 5 process corners were functional with supply voltage as low as 0.28V.

PVT‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

Abstract: In this paper, a low‐noise amplifier (LNA) with process, voltage, and temperature (PVT) compensation for low power dissipation applications is designed. When supply voltage and LNA bias are close to the subthreshold, voltage has significant impact on power reduction. At this voltage level, the gain is reduced and various circuit parameters become highly sensitive to PVT variations. In the proposed LNA circuit, in order to enhance efficiency at low supply voltage, the cascade technique with gm boosting is used. To improve circuit performance when in the subthreshold area, the forward body bias technique is used. Also, a new PVT compensator is suggested to reduce sensitivity of different circuit's parameters to PVT changes. The suggested PVT compensator employs a current reference circuit with constant output regarding temperature and voltage variations. This circuit produces a constant current by subtracting two proportional to absolute temperature currents. At a supply voltage of 0.35 V, the total power consumption is 585 μW. In different process corners, in the proposed LNA with PVT compensator, gain and noise figure (NF) variations are reduced 10.3 and 4.6 times, respectively, compared to a conventional LNA with constant bias. With a 20% deviation in the supply voltage, the gain and noise NF variations decrease 6.5 and 34 times, respectively.

3.5 A 34µW 32MHz RC Oscillator with ±530ppm Inaccuracy from −40°C to 85°C and 80ppm/V Supply Sensitivity Enabled by Pulse-Density Modulated Resistors

Abstract: Monolithic frequency references built using on-chip time constants are gaining popularity as possible replacements to bulky quartz-crystal or MEMS-based oscillators in low-cost applications. Among them, RC time-constant-based references [1]–[4] are most attractive because they occupy a small area, consume little power, and are well suited for integration in any standard CMOS process. But their performance is very susceptible to variations in temperature and supply voltage. Frequency-locked-loop(FLL)-based closed-loop RC oscillators [2]–[4], compared to open-loop relaxation oscillators, have higher immunity to voltage variations. However, their performance is also limited by the temperature dependence of the resistor. This limitation was addressed in the prior art by using a composite resistor made from resistors with opposing temperature coefficients (TCs) [2]. Unfortunately, the TC of the composite resistor is highly dependent on process-sensitive sheet resistance of resistors comprising it. So, it is typically implemented using a vast array of resistors that are trimmed on a sample-by-sample basis. While this approach helps to alleviate process sensitivity, two critical factors limit the achievable frequency inaccuracy to about 5000ppm. First, the accuracy with which the TC is canceled across process corners is fundamentally limited by the finite number of resistor combinations that can be practically implemented on a chip. Second, leakage currents in the switches used to select the resistors along with the mixing of TCs of individual resistors in the array generate large higher-order TCs that are difficult to compensate. Recently reported voltage-ratio adjusting [2] and polynomial-based [3] higher-order compensation schemes lowered frequency inaccuracy to about 500ppm. However, they either rely on precise combinations of analog voltages and are therefore sensitive to circuit-level imperfections or occupy a large area and exhibit poor power efficiency (100µW/MHz) [3].

A 0.7-V, 192 pA Current Reference with 0.51%/V Line Regulation for Ultra-Low Power Applications

Abstract: A 192 pA current reference is proposed for ultra-low-power applications. The sub-threshold design based circuit employs three-transistor-regulators to provide a CTAT (complimentary-to-absolute-temperature) source to gate voltage, to a PMOS device that minimizes the temperature variation of the reference current. Consistent performance across process variations is achieved through digital trimming and body bias control. A temperature coefficient (TC) of 542 ppm/ °C is attained at nominal process with a minimum and maximum TC of 350 ppm/ °C and 729 ppm/ °C, respectively, across all process corners. The circuit operates at a worst case minimum supply voltage of 700 mV and the power consumption is 1.06 nW at the nominal process and temperature. The same architecture is reused for a reference current of 87.7 nA, which improves the TC to 91.2 ppm/ °C. The circuit is designed in standard 0.18 μm CMOS technology.

Efficient Parametric Yield Estimation Over Multiple Process Corners via Bayesian Inference Based on Bernoulli Distribution

Abstract: Parametric yield estimation over multiple process corners plays an important role in robust circuit design. In this article, we propose a novel Bayesian inference method based on Bernoulli distribution (BI-BD) to efficiently estimate the multicorner yields for binary output circuit. The key idea is to encode the circuit performance correlation among different corners as our prior knowledge. Consequently, after combining a few simulation samples, the yield estimation over all corners can be calibrated via Bayesian inference based on iterative reweighted least squares (IRLS) and expectation maximization (EM). A circuit example demonstrates that the proposed BI-BD method can achieve up to $2.0\times $ cost reduction over the conventional Monte Carlo method without surrendering any accuracy.

A 90-nm 640 MHz 2 × VDD Output Buffer With 41.5% Slew Rate Improvement Using PVT Compensation

Abstract: This brief presents a 2 $\times $ VDD output buffer using the encoded compensation technique to minimize slew rate (SR) deviation caused by PVT (process, voltage, temperature) variations. The process detectors can both detect all five process corners and ensure the compensation code unchanged in VT variations. Besides, the charging paths of the proposed voltage level converter (VLC) are independent and directly driven by logic gate, which applied in output stage to speed output buffer data rate up. The proposed design is implemented using a typical 90 nm 1.2 V 1P9M CMOS process, where the core area of a single output buffer is $400\,\,\mu \text{m}\times 56\,\,\mu \text{m}$ . The measured maximum data rate is 640/480 MHz given 1.2/2.5 V supply voltage, and the power consumption is 32.2 mW at 640 MHz data rate. the slew rate variation improvement is 41.5%/41.9% by PVT detection and SR compensation for VDDIO=1.2/2.5 V, respectively.

A Novel High Speed, Low Power, and Symmetrical Phase Frequency Detector with Zero Blind Zone and π Phase Difference Detection Ability

Abstract: This paper presents a novel symmetrical phase frequency detector (PFD) sensitive to the falling edge of input clocks. Notably, the new PFD has an open-loop structure and no reset path, since UP and DN (outputs of the PFD) are never allowed to reach logic high simultaneously. Hence, the blind zone is completely eliminated in this case. Dead zone has been reduced to a great extent about 68 fs. Meanwhile, the proposed PFD is reliably capable of detecting from 0° to 360°, even 180° phase difference between clocks correctly by itself. The PFD has been simulated using the H-SPICE level 49 of a standard 0.18 μm CMOS process. It has been simulated in different conditions. Its maximum operating frequency at the worst-case conditions varied from 1.4 to 4.7 GHz at different supply voltages varied from 1.2 to 2.4 V. It can operate from very low frequencies up to 4.3 GHz at the power supply of 1.8 V, reliably. It can be used in high-speed and low-power applications. The new PFD consumes power within a range from 11.79 to 478.8 μW when operating at 50 MHz and 4.3 GHz, respectively. It has also been simulated in different process corners. Using the minimum size devices leads to a compact layout and die size of about 124.3 μm2.

0.5 V Two-Stage Subthreshold Fully Differential Miller Compensated OTA Using Voltage Combiners

Abstract: A simple high-performance architecture for low-voltage and power-efficient gate along with bulk-driven miller compensated Fully Differential Operational Transconductance Amplifier (FDOTA) for biomedical applications is presented in this paper. The proposed design is suitable for operation under sub-1 V single supply and consists of two gain stages. Voltage Combiner (VC) based pseudo-differential circuit has been used in the second stage in order to increase the DC gain. In the proposed design, all the MOSFETs are biased to operate in the subthreshold region for minimum power consumption. The OTA is implemented in the Cadence Virtuoso Environment using 180 nm standard CMOS technology under 0.5 V and consumes only 70nW power. DC gain, Unity Gain Bandwidth (UGB), and phase margin are found to be 68.0656 dB, 9.395 kHz, and 71.90425°, respectively at a capacitive load of 5 pF. The minimum input-referred noise at 10 Hz and 10 kHz frequencies is found to be 4.6161 µV/sqrtHz and 276.323 nV/sqrtHz, respectively. The OTA is simulated for different process corners and temperature variations also.

Design of Low Power 7T SRAM Cell for portable Biomedical Applications

Abstract: In various medical applications, electronic devices are remaining as an integral part, where one of these applications is body area networks (BAN), which have networked sensors to monitor different physiological parts of human body. These BAN`s require efficient power capability with SRAM to handle data. In this paper, an 18nm FinFET based 7T SRAM cell is proposed to address the challenges on power and stability. In order to reduce the power leakage, the FinFET based 7T SRAM cell is designed by using self-controllable voltage level techniques that reduce leakage power to 92% in comparison to other SRAM. The process corner analysis is done using Cadence Virtuoso using 18nm FinFET technology, at lower temperature data retention voltage is lowest at the fs process corner and highest at FF Corner, and at the highest temperature, the value of data retention voltage is high at FF Corner.

A 0.1–2.75 GHz high-linear low-noise transconductance amplifier for high-performance multi-standard wireless applications

Abstract: The frequency bands below 3 GHz are occupied by various wireless applications. The overcrowding of many applications in these bands is the primary source of distortion in the wireless system. To combat distortion in the system, the radio frequency (RF) blocks must satisfy the linearity requirements of the application. Hence, in this paper, a high linear wideband low noise amplifier (LNA) stage is proposed for RF front-end. The LNA uses the combination of common-gate (CG) and common-source (CS) stages for cancelling the noise and distortion of the input matching CG stage. The CS stage exploits complementary derivative superposition (CDS) for linearity improvement, and cross-coupled local feedback network is employed for noise cancellation at the output. The LNA stage is designed using UMC 180 nm CMOS process technology and post-layout characterizations are carried out using Cadence SpectreRF circuit simulator. Also, the process corner, voltage, and temperature (PVT) variation analysis and Monte-Carlo simulations for mismatch analysis are carried out to verify the reliability of the LNA. The designed LNA has an input referred third-order intercept point (IIP3) of 8.85 dBm. The proposed LNA has a maximum gain of 23.96 dB and minimum noise figure (NF) of 1.4 dB with a total current consumption of 3.1 mA from a 1.8 V supply.

A Learning-Based Timing Prediction Framework for Wide Supply Voltage Design

Abstract: Wide voltage design provides the tremendous benefits for state-of-the-art circuit design in terms of power consumption reduction and energy efficiency enhancement. The traditional design and verification flow depends on the standard cell libraries, which are only available from foundries for limited PVT (Process-Voltage-Temperature) corners near the nominal voltages, leading to remarkable characterization effort and storage overhead. In this paper, a learning-based framework is proposed to predict circuit path delays across multiple voltages and process corners without the requirement of cell library for each PVT corner, which consists of dilated-CNN (Conventional Neural Network) based feature engineering and ensemble model. The proposed method was verified with the supply voltages ranging from 0.5V to 0.9V under FF, SS and TT corners. Experimental results demonstrate that the prediction error is limited by 4.9% and 7.9% respectively within and across process corners for various working temperatures, which achieves significant precision enhancement compared with related learning-based methods.

A voltage-adjustable output-capacitorless LDO regulator with split-length current mirror compensation and overshoot/undershoot reduction

Abstract: An output-capacitorless low-dropout regulator (OCL-LDO) using split-length current mirror compensation and overshoot/undershoot reduction circuit are presented in this paper. At a supply of 1.5 V and a quiescent current of 8.2 µA, the proposed scheme can support a maximum load current of 50 mA. The proposed OCL-LDO has a range of output voltage from 0.8 to 1.25 V with 1.5 V supply. The proposed regulator is designed and post-simulated by UMC 55-nm standard CMOS process. The simulation results show that the proposed scheme is stable in different temperatures and process corners with 10 pF output capacitor. The maximum value of overshoot and undershoot is 69.0 mV and 91.5 mV, respectively.

67ppm/°C, 66nA PVT Invariant Curvature Compensated Current Reference for Ultra-Low Power Applications

Abstract: This work presents a highly accurate current reference of 66nA for ultra-low power applications. A very low figure-of-merit (FOM) of 1.3501ppm/°C2 is achieved on consuming a minimal quiescent current of 199.37nA. To cancel out process variations, the current subtraction technique is employed and a β-multiplier is used to compensate for mobility (μ) and threshold voltage (V th ). In addition, curvature compensation technique backed by PTAT and CTAT current cancellation is adopted to attain a lower temperature coefficient (TC). Hence, an imperceptible variation of accuracy with temperature and supply variations across all process corners is attained. An adopted trimming scheme further minimizes the overall process spread to ±1.515% without compromising on accuracy. Accordingly, a TC of 67.04ppm/°C over a wide temperature range of −50° C to 100° C is obtained. Furthermore, 1.413%/V line sensitivity (LS) in the supply range of 1.38V to 3V is observed. Low power consumption of 275.13nW@1.38V facilitates its use in high-performance low power applications.

An Accurate and Efficient Timing Prediction Framework for Wide Supply Voltage Design Based on Learning Method

Abstract: The wide voltage design methodology has been widely employed in the state-of-the-art circuit design with the advantage of remarkable power reduction and energy efficiency enhancement. However, the timing verification issue for multiple PVT (process–voltage–temperature) corners rises due to unacceptable analysis effort increase for multiple supply voltage nodes. Moreover, the foundry-provided timing libraries in the traditional STA (static timing analysis) approach are only available for the nominal supply voltage with limited voltage scaling, which cannot support timing verification for low voltages down to near- or sub-threshold voltages. In this paper, a learning-based approach for wide voltage design is proposed where feature engineering is performed to enhance the correlation among PVT corners based on a dilated CNN (convolutional neural network) model, and an ensemble model is utilized with two-layer stacking to improve timing prediction accuracy. The proposed method was verified with a commercial RISC (reduced instruction set computer) core under the supply voltage nodes ranging from 0.5 V to 0.9 V. Experimental results demonstrate that the prediction error is limited by 4.9% and 7.9%, respectively, within and across process corners for various working temperatures, which achieves up to 4.4× and 3.9× precision enhancement compared with related learning-based methods.

Current Reference Circuit Operable at Low Voltages Using Composite MOS Triode Resistor

Abstract: Invasive biomedical applications involving acquisition and recording of biological signals require current reference generation circuits for low voltage front-end amplifier and filter circuits. However, achieving current reference using Self-Biased Current Source (SBCS) for these circuits at same low supply voltages poses requirement of resistors. In this work, we compare the effect of passive poly resistor and Composite Triode MOS Resistor (CTMR) on the performance of low voltage SBCS circuit using 0.18 µm standard SCL foundry process parameters and models of MOS, capacitor and resistor. For current reference generation of 371 nA, the temperature coefficient (ppm/degree Celsius) values for passive poly resistor and CTMR are 2400 and 2251 respectively. The Figure of Merit, FOM (ppm/degree Celsius) and Coefficient of variance (CV) at different process corners with Monte-carlo simulation (MCS) runs of 100 for CTMR are 0.93 and 0.16 times lower than that of passive poly resistor. The CTMR based SBCS is anticipated to be used in low voltage front-end biomedical applications.

A wide tuning range, low noise oscillator with FoM of -188 dBc/Hz in 45 nm CMOS

Abstract: A wide tuning range, low phase noise oscillator with 3 stage differential configuration is presented. GPDK 45 nm CMOS Technology is selected for the design and simulation of the proposed circuit, under power supply impediment of 1.1 V. Proposed delay cell features ultra wide tuning range as it utilizes dual control voltages ( V c 1 and V c 2 ), enabling large current to flow in the circuit. As frequency of oscillation has linear proportionality with the bias current, this oscillator generates frequencies from 534 MHz to 18.56 GHz. The proposed circuit occupies chip area of 102 . 87 μ m 2 . This circuit offers power consumption of 1.13 mWatt and phase noise of − 108 . 61 dBc/Hz (10 MHz offset frequency) at 5.82 GHz oscillation frequency. Performance of the proposed circuit is evaluated on various temperature, supply voltage and process corners. Total Harmonic Distortion (THD) profile is also measured through simulation. Because of wide frequency spectrum, low phase noise, small area and low power budget, proposed circuit can be utilized in various power electronic applications, medical equipments, communication and navigation systems.

Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation

Abstract: Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed. The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V. The method used to verify the robustness of the comparator circuit across 45 PVT is presented. The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 100°C. The simulation result show that the proposed comparator circuit achieved significant reduction of power consumption and delay during worst case condition compared to dynamic comparator proposed from previous researchers.

Robust linear sampling switch for low-voltage SAR ADCs

Abstract: This paper presents a linear sampling switch for low-voltage successive-approximation register (SAR) analogue-to-digital converters (ADCs) operating at a frequency of tens of MHz. The proposed switch employs a bootstrapped transmission gate, where the bulk voltages are generated internally to minimize variations in the threshold voltage of transistors with input signal amplitude. Thus, ensuring almost constant and low ON-resistance ($$R_{ON}$$) over complete input signal range without using wide transistors, charge pumps, or both, at low supply voltages. The proposed switch was designed using standard 65 nm CMOS technology. The post-layout simulations have shown a signal to noise and distortion ratio (SNDR) of 87.81 dB, a spurious-free dynamic range (SFDR) of 90 dB and a total harmonic distortion (THD) of $$-91.5\,\hbox {dB}$$ at a sampling frequency and supply voltage of 100 MHz and 0.8 V, respectively. In addition, the switch has shown a maximum variation of 1% in $$R_{ON}$$ over input signal amplitude at different process corners and temperature, which is low compared to other sampling switches reported in the literature.