Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Performance Analysis of Full Adder Circuit using Conventional and Hybrid Techniques

Abstract: Adders are widely used in many digital circuits and play an integral role in the implementation of various logic circuits. From the starting days, efforts are being made to design the circuit with fewer numbers of transistors. In VLSI design speed, area and power always have trade-offs. The conventional full adder requires 32 transistors (32T) to implement. This circuit gives superior performance in terms of speed but consumes a lot of area and power. Efforts are being made by various means to decrease the number of transistors to design the same logic which will help to achieve a similar or better speed with lesser power and area consumption. We analyzed and compared the full adder circuit using 28T, 20T, 18T, 14T, and 10T. The analysis is done on Cadence Virtuoso at 45nm, 90nm, and 180nm technology nodes using generic process design kit (gpdk) CMOS cell libraries. The comparison is done based on three key parameters that are speed, area, and power consumed by the circuit. The process corner analysis and post-layout simulation are performed on 45nm technology for three circuits which are good at one key parameter between power, delay, and area.

Modeling of MOS Matching

Abstract: Circuit operation greatly depends on the ability to control and reproduce transistor and process parameters, such as oxide thickness, dielectric constants, doping levels, width and length. Variation in processing was in the past countered by defining process corners: boundaries in parameter variation that accounted for remaining process tolerances. With the improved control over processing, this batch-to-batch variation is largely under control.

On the use of wafer positional and spatial pattern analysis to identify process marginality and to de-convolute counterintuitive experimental results

Abstract: The use of wafer randomization and positional analysis in manufacturing is ubiquitous and well established. Wafer electrical and yield data can be traced back to specific operations in the manufacturing process with the help of wafer sequencing records. Tight process windows or complex process technologies may however require that the statistical parameter versus sequence signal be combined with other variables including parameter spatial distribution on wafer, batch loading sequence, and an intimate knowledge of the process tool itself. In this paper case studies are presented to demonstrate how the above were combined to optimize the robustness of an especially critical gate oxidation process module. Finally possible enhancements to analysis techniques are discussed.

Semiconductor integrated circuit device and semiconductor device including plurality of semiconductor circuits

Abstract: A semiconductor integrated circuit device includes a first semiconductor circuit, a second semiconductor circuit, a first control circuit and a second control circuit. The first and second semiconductor circuits are formed on a semiconductor substrate and operate using a voltage provided by an external power supply circuit as a power supply voltage. The first control circuit is formed on the semiconductor substrate and holds control information used to control the voltage generated by the external power supply circuit in accordance with operating performance of the first and second semiconductor circuits. The second control circuit controls a property of the first semiconductor circuit in accordance with the control information held by the first control circuit.

An all-n-type dynamic adder for ultra-low-leakage IoT devices

Abstract: Ultra-low leakage is demanded for low-duty-cycled IoT applications. An NP-type dynamic ripple-carry adder (NP-RCA) was shown outperforming the static design in terms of energy based on pre-layout simulations. We will show that the NP-RCA suffers from serious parasitic RC effects. We then propose an all-N-type RCA (All-N-RCA) in this work to reduce the influence of parasitic effects to achieve a much higher speed with a much lower leakage current. All the designs are evaluated according to post-layout simulation results in 28 nm CMOS. For an IoT application with a 0.02% duty cycle, the 32b All-N-RCA achieves a 57% energy reduction compared to the static counterpart at the typical process corner.