Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

A methodology for efficient design of analog circuits using an automated simulation based synthesis tool

Abstract: We present a methodology for efficient design of analog circuits using an automated simulation based synthesis tool. In this methodology, the designer chooses a suitable circuit topology and defines the performance criteria of the circuit. The synthesis tool provides optimized device dimensions which guarantees that the circuit meets the specified performance criteria across process corners. This methodology is independent of the circuit type (as long as the performance criteria can be quantified and measured from simulation data), the fabrication process being used, and also the circuit simulator of choice. We show that this design methodology reduces the design cycle time by a significant amount and helps analysing the trade off between different performance criteria. It also helps in analysing the suitability of several alternative topologies for a given purpose in a short time. In this paper we substantiate this claim with the help of an operational amplifier design.

Layout-aware through-process circuit analysis

Abstract: In the post-90 nm era, due to the advent of low-K1 lithography, variability of circuit parameters, such as effective gate-length and gate-width, is increasing. In this paper, we illustrate how we perform layout aware through process circuit analysis using simulated wafer contours and present results for a full-custom 4:2 compressor circuit.

Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors

Abstract: A common concern as we scale down transistor threshold voltages while migrating to new process technologies is the requirement to achieve timing closure within a given power budget over various process corners. High performance microprocessors are designed keeping in mind the various process technologies, application space and multi-site fabrication requirements. Described here is an optimization methodology and a unique topology-aware heuristic algorithm employed for high speed microprocessor designs capable of simultaneous threshold voltage selection for library cells across various technology process corners. The algorithm uses knowledge of the circuit topology rather than considering only the immediate local connectivity as is suggested in other heuristic methods and evaluates timing criticalities originating from different input and output logic cones associated with every pin of a failing path. The VTH selection is done so as to affect multiple failing paths with each low VTH cell selection, hence reducing leakage power. Two sets of algorithms are used alternately. One takes advantage of the circuit topology to address multiple failing paths simultaneously. The other performs a fine tuned optimization that has more granularity while considering a particular failing path. This flow is not limited to dual threshold VTH selection but can also support the use of multi-VTH library cells. This flow and its algorithms reduced the usage of low VTH in a particular multi-million transistor design from 35.3% to 10.7% without any loss of performance thus resulting in a 55.6% drop in leakage power. Reducing the usage of lower VTH cells results in significant power reduction. This reduction in power could also allow running the chip at a higher VDD and frequency within the original power envelope. Production results from this tool exceeded the optimization efforts of another commercially used EDA optimization tool.

A high-precision ultra-low-power hysteretic voltage detector for energy harvesting system

Abstract: A high-precision ultra-low-power, hysteretic voltage detector (HVD) featuring temperature and process insensitivity is presented in this paper. In order to improve its thermal stability, a temperature-independent current is generated by a special voltage-controlled current source. The current is compared with a reference current to determine the start-up voltage of hysteresis window. And a Schmitt inverter is served to provide the hysteresis window. Besides, a current pre-amplifier is developed to enhance the HVD's response to small changes of the detected voltage. The HVD is designed and fabricated in SMIC 0.18 µm CMOS process. The simulation results show that its hysteresis window is about 0.02V. And the sensitivity to temperature and process corners are about 347ppm/°C and −1.5%∼2.3% respectively. In addition, the HVD can response precisely to as low as 1mV variation around the switching voltage. The total power consumption of this HVD is only 840nW at 1.8V supply voltage.

Current Reference Circuit Operable at Low Voltages Using Composite MOS Triode Resistor

Abstract: Invasive biomedical applications involving acquisition and recording of biological signals require current reference generation circuits for low voltage front-end amplifier and filter circuits. However, achieving current reference using Self-Biased Current Source (SBCS) for these circuits at same low supply voltages poses requirement of resistors. In this work, we compare the effect of passive poly resistor and Composite Triode MOS Resistor (CTMR) on the performance of low voltage SBCS circuit using 0.18 µm standard SCL foundry process parameters and models of MOS, capacitor and resistor. For current reference generation of 371 nA, the temperature coefficient (ppm/degree Celsius) values for passive poly resistor and CTMR are 2400 and 2251 respectively. The Figure of Merit, FOM (ppm/degree Celsius) and Coefficient of variance (CV) at different process corners with Monte-carlo simulation (MCS) runs of 100 for CTMR are 0.93 and 0.16 times lower than that of passive poly resistor. The CTMR based SBCS is anticipated to be used in low voltage front-end biomedical applications.