Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Current mode logic circuits with automatic sink current adjustment

Abstract: Integrated circuit devices may utilize automatic methods for adjusting the tail currents of current mode logic (CML) cells, which compensate for variations in process corners and thereby enable reliable operation of high performance circuits, such as frequency synthesizers. An integrated circuit may include a current mode logic (CML) circuit responsive to at least one input signal and a variable current source electrically coupled to the CML circuit. This variable current source can be configured to sink (or source) a first current from (or to) the CML circuit in response to a control signal. A control circuit may also be provided, which is configured to generate the control signal in response to a process corner indication signal. This process corner indication signal, which may be generated by a process corner detection circuit, preferably has a magnitude that estimates a relative speed of a process corner associated with the integrated circuit device.

Method and apparatus for manufacturing semiconductor integrated circuit device

Abstract: The present inventors have found that a wafer process of VLSI (Very Large Scale Integration) has the following problem, that is, generation of foreign matters due to moisture from a wafer as a result of degassing when a barrier metal film or a first-level metal interconnect layer is formed by sputtering as a preliminary step for the formation of a tungsten plug in a pre-metal step. To overcome the problem, the present invention provides a manufacturing method of a semiconductor integrated circuit device including, in a plasma process, in-situ monitoring of moisture in a processing chamber by receiving an electromagnetic wave generated from plasma.

Design of a temperature-insensitive digitally-controlled oscillator for on-chip reference clock

Abstract: This paper presents a 0.4V temperature-insensitive digitally-controlled ring oscillator (DCO) for on-chip reference clock circuit. Based on a modified bootstrapped ring oscillator (BTRO), temperature variation can be further decreased without calibration, where BTRO is operated at near-threshold voltage. A binary-weighted tree-controlled resistor network (BWTRN) is performed to achieve an 8bit high-linearity DCO with BTRO. The proposed DCO is fabricated in TSMC 90 nm CMOS process with a core area of 0.013 mm2. The simulation results in typical corner demonstrate that the DCO oscillates max/min frequency of 105.6MHz/60.7MHz at 0.4 V V dd and consumes 8.77μW/4.44μW. The maximum temperature variation of the single code is 329 ppm, and its maximum DNL variation is 0.67 LSB. Even for all process corners, the maximum temperature variation among all control codes is 8%.

An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI

Abstract: In advanced technology nodes, device variations limit the SRAM performance and yield. Cell stability defined by the Static Noise Margin (SNM) of the SRAM cell primarily governs the performance with respect to yield in SRAMs. Variations in the scaled SRAMs increase the probability of cells becoming weak. To ensure reliability of SRAMs it is important to identify such cells post silicon. In this work, we propose a correlation based test methodology to detect the weak bits in SRAMs with respect to SNM. We present a case study for 64×64 SRAM in 28nm FDSOI technology. The proposed methodology targets high speed testing and lower test costs. It enables to perform the test at nominal operating voltage and room temperature. Suitable read stress is induced by boosting the Word Line (WL) voltage of the 6T SRAM cell. To validate the effectiveness of the test and find appropriate test stress we propose correlation methodology. With this test we could detect the weak cells possessing SNM upto 60mV across various process corners for stress voltage ranging from 1.14V to 1.16V. Moreover, it requires minimal area penalty and test time compared to standard tests.