Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Design of SiGe BiCMOS LNA with ESD Protection for Multi-band Navigation Receiver Front-End

Abstract: An ESD protected, SiGe BiCMOS wide-band LNA operating at 1.1—1.7GHz is presented in this paper. The cascoded common-emitter LNA with an LC input matching network and shunt peaked load is adopted. The effects of the ESD protection on the performance are discussed. The LNA is implemented in a 0.35-μ m SiGe BiCMOS process with fT = 45G Hz. The post simulation results show that the noise figure is 1.7dB with a high S21 (22.5dB) and IIP3 of -17dBm, consuming total current of 8.1mA with an output buffer. The circuit is simulated under the combination of process corners and variation of temperature and power supply voltage.

Semiconductor integrated circuit inspection device and semiconductor integrated circuit inspection method

Abstract: PROBLEM TO BE SOLVED: To easily determine a non-defective/defective of a semiconductor integrated circuit without executing logic simulation and failure simulation. SOLUTION: A plurality of resistors 2 having a prescribed resistance value are connected to a plurality of output terminals OUT of the semiconductor integrated circuit 1, and a prescribed voltage is impressed to the plurality of resistors 2. A prescribed operation pattern signal for inspecting a function of the semiconductor integrated circuit 1 is input to a plurality of input terminals IN of the semiconductor integrated circuit 1. Total of current amounts flowing respectively in the plurality of resistors 2 is measured thereby. The measured total of the current amounts is compared with a normal value in total of current amounts measured using a nondefective sample with a normal operation confirmed preliminarily in place of the semiconductor integrated circuit 1, and the propriety of the normality of the semiconductor integrated circuit 1 is determined based on a result therein. COPYRIGHT: (C)2005,JPO&NCIPI

A 0.5 V Low Power DTMOS OTA-C Filter for ECG Sensing Applications

Abstract: This paper presents a 0.5 V ultra-low power Gm - C fourth order low pass filter with Butterworth response for ECG detection. An Operational Transconductance Amplifier (OTA) forms the basic building block of the filter. In order to achieve high performance at low power, the G m cell has been designed using Dynamic Threshold MOS (DTMOS) in 180 nm CMOS N-well technology. A hybrid design that uses a DTMOS pseudo differential architecture with G m reduction enables the OTA to operate at 0.5 V achieving a transconductance as low as 0.25 nS, which cuts down the area of large on-chip capacitance significantly for low frequency applications. The designed filter has a cutoff frequency of 7.3 Hz with a total power consumption of 29.7 nW. The simulated variation of the achieved cutoff frequency over the process corners is less than ± 10 %.

A novel approach for noise tolerant energy efficient TSPC dynamic circuit design

Abstract: A dynamic circuit design technique on the basis of true single phase logic is presented in this paper to minimize leakage power consumption. The circuit is comprehensively designed by incorporating a pair of diode transistor and a pair of stacked transistors. Active mode as well as idle mode power consumption and delay is analysed at low and high die temperature. 89–17% saving in power delay product is obtained for the same along with higher unity noise gain and reduced voltage bouncing noise. The analysis of the circuit also includes the investigation of voltage variation effect, process corner analysis and sizing effect analysis. The proposed technique is compared with several previously proposed dynamic circuit design techniques and it is found to have best power delay product. Further, it is implemented on 32 output decoder for enduring the technique. Comprehensive simulation using 90 nm technology in cadence specter, shows that the proposed design vanquish conventional and other previously proposed dynamic circuit design techniques in terms of power, delay, noise and robust against parameter and process corner variations.

Defect inspection apparatus for electronic circuit

Abstract: PROBLEM TO BE SOLVED: To locate a defective in an electronic circuit by applying a voltage to this circuit through a probe and moving the probe, relative to a semiconductor wafer to detect the heating state of the circuit with the applied voltage. SOLUTION: A defect inspection apparatus has a test stage to test an electronic circuit on a semiconductor wafer 1 supported on the stage, and a voltage is applied to this circuit on the wafer through a probe 3 connectable to the electronic circuit. A drive mechanism changes the relative position of the probe 3 to the wafer 1. When the voltage is applied from the source 4 to the electronic circuit on the wafer, a thermal image of the circuit (infrared image) is focused on a solid-state image sensing element of an infrared detector 14 to photoelectrically convert it into an image data which is taken out and transferred to an image processor 11 to process it by the intensity modulation, etc. COPYRIGHT: (C)1997,JPO