Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

A transistor-based clock jitter insensitive DAC architecture

Abstract: A decaying pulse shape DAC architecture for continuous-time (CT) /spl Sigma//spl Delta/ modulators is introduced. The DAC reduces the clock jitter sensitivity while putting only moderate design constrains on the respective integrators. The impact of clock jitter on the entire /spl Sigma//spl Delta/ modulator is computed and verified by electrical and behavioral simulations. In order to illustrate also the low-power benefits, the required integrator gain-bandwidth is evaluated and the obtained results are compared with corresponding simulation results. The DAC is implemented in a 1.8V 0.18/spl mu/m CMOS process operating at a sampling frequency of f/sub S/=200MHz. The effect of process corners, supply voltage and temperature (PVT) is illustrated. Finally, various design constrains are discussed.

SICE: design-dependent statistical interconnect corner extraction under inter/intra-die variations

Abstract: While traditional worst-case corner analysis is often too pessimistic for nanometer designs, full-blown statistical circuit analysis requires significant modelling infrastructures. In this study, a design-dependent statistical interconnect corner extraction (SICE) methodology is proposed. SICE achieves a good trade-off between complexity and pessimism by extracting more than one process corners in a statistical sense, which are also design dependent. Our new approach removes the pessimism incurred in prior work while being computationally efficient. The efficiency of SICE comes from the use of parameter dimension reduction techniques. The statistical corners are further compacted by an iterative output clustering method. Numerical results show that SICE achieves up to 260X speedups over the Monte Carlo method.

A circuit design and fabrication approach to address global process variation

Abstract: This paper proposes a new approach for reducing the consequences of global process variation and improving integrated circuit yield. In the proposed technique, a design of a given circuit block is optimized for multiple process corners, giving rise to multiple sub-designs. The sub-designs are constructed such that all can be implemented using the same front-end-of-the-line mask steps, and having back-end-of-the-line processing differing by as few as one mask step (e.g., the Via1 layer). During fabrication, in-line measurements made after the first level of metal deposition determine which sub-design is fabricated through the appropriate selection of the mask step variant. The technique allows for per-wafer or per-reticle circuit customization based on the wafer's or reticle's process parameters. A tapered buffer chain is investigated as an example of the technique. Simulation results show yield improvements of up to 20% and reductions in power dissipation up to 18%.

Comparison of LC-VCO and LC-DCO parameters in 65 nm CMOS technology

Abstract: In this paper the performance of frequency oscillators is analyzed in different types of oscillators LC-VCO and LC-DCO CMOS integrated circuit (IC) technology nodes is the same − 65 nm Both oscillators are based on cross-coupled NMOS topology and are designed with Cadence IC software package All parameters are obtained by simulating the scheme under nominal conditions (supply voltage 18 V, temperature 60 °C, nominal technological process corner)

A robust to PVT variations low-voltage low-power current mirror

Abstract: In this paper the design of a very low-voltage current mirror with an enhanced output resistance is presented. The mirror is designed using transistors in weak-inversion region, which allows operating with reduced supply voltage. With the use of multiple feedback loops, parameters such as minimum output voltage and output resistance are kept constant with respect to supply voltage, temperature and fabrication process variations (PVT variations). The mirror is biased at 0.5 V and is designed in a standard 0.18 μm technology. As a result, the circuit needs only 60 mV and 80 mV to saturate for NMOS and PMOS implementations respectively, with a maximum variation of 10 mV for all process corners and temperatures between −40 °C and 120 °C, and supply voltages between 0.45 V and 0.55 V. Finally, the mirror was used in a one-stage fully-differential OTA, for which a gain of 75 dB was achieved.