Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

PVT variation detection and compensation circuit

Abstract: A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit includes a signal generator, a first code generator, a second code generator, and a mapping module. The signal generator generates a first signal and a second signal depending on aligned process corner, voltage and temperature variations and skewed process corner variations respectively. The first code generator receives the first signal, and generates a first calibration code. The second code generator receives the second signal, and generates a second calibration code. The mapping module provides the first and second calibration codes for compensating for the aligned process corner, voltage and temperature variations and the skewed process corner variations associated with the functional modules respectively.

Semiconductor integrated circuit apparatus, measurement result management system, and management server

Abstract: A semiconductor integrated circuit apparatus, and more particularly a technology for measuring and managing a physical amount of factors that exert an influence upon an operation of a semiconductor integrated circuit is provided; more particularly, a semiconductor integrated circuit that is an object of measurement, and a measurement circuit which measures a physical factor that exerts an influence upon the actual operation of the semiconductor integrated circuit, such as jitter or noise jitter, and noise of this semiconductor integrated circuit are provided on an identical chip; also, a measurement result of the measurement circuit of the present invention is analyzed, and is fed back to a circuit for adjusting the semiconductor integrated circuit that is the object of measurement.

Compact Analytical Model to Extract Write Static Noise Margin (WSNM) for SRAM Cell at 45-nm and 65-nm Nodes

Abstract: The operation of static random access memory (SRAM) in the subthreshold region reduces both leakage power and access energy. Subthreshold operation is one of the proficient techniques to accomplish low-power and high performance system on chip. But the challenge, in subthreshold SRAM design, is the SRAM stability. The sensitivity to process variations increases with technology scaling resulting in reduced stability. In this paper, SRAM write stability is analyzed in the subthreshold region. The semi-analytical model of write static noise margin (WSNM) for 6T SRAM (subthreshold region) has been given in this paper. The results obtained from the analytical model are verified through simulations in Cadence using GPDK 45-nm, UMC 65-nm, and UMC 130-nm technology files. The model is based on the subthreshold current equations of the transistor. Further, the write stability of the SRAM is analyzed with the varying supply voltage and the sizing ratios. The process corner analyses is also accomplished to verify the write stability of the SRAM cell using the model at the worst process corners. To the best of the author’s knowledge, this is the first model to analyze the WSNM based on the traditional butterfly static noise margin approach. It has been observed that the model is valid for all of the technology nodes, i.e., at 45 nm, 65 nm, as well as 130 nm. Also the model holds well for 8T and 10T SRAM configurations in addition to 6T SRAM cell.

Entropy and Energy Bounds for Metastability Based TRNG with Lightweight Post-Processing

Abstract: On-chip True Random Number Generators (TRNG) are important cryptographic primitives in a variety of applications. In advanced CMOS process technologies, intra-die variations in transistor parameters bias the TRNG and degrade the statistics of the bit stream generated. In this work, we present a stochastic model for metastability based TRNG circuit incorporating both the impact of intra-die variations and thermal noise. The stochastic model is used to estimate the expected entropy out of a TRNG at a given process corner for variations in channel length and threshold voltage. We use the stochastic model to study the impact of variations on three lightweight post-processing techniques: von Neumann corrector, XOR function, and PRESENT cipher. The expected bit rate out of von Neumann corrector, number of XOR stages required for entropy extraction and the number of iterations for using PRESENT encryption are estimated for various process corners using the probabilistic entropy values. These analyses are further extended to different device sizing and operating voltage to explore the optimum trade-off between entropy extraction and energy overhead. A combination of HSPICE circuit simulation using 32 nm Predictive Technology models and stochastic modeling in MatLab show that XOR function and von Neumann corrector have an energy overhead ranging from 0.012pJ/bit to 0.15pJ/bit at the cost of decreased yield and bit-rate respectively. PRESENT cipher provides robust entropy extraction by increasing the number of encryption iterations from 1 for $\mu/\sigma(Leff) to 3 for $\mu/\sigma(Leff)>8\%$ . With a maximum of 2.52pJ/bit PRESENT provides a more energy efficient solution compared to AES for entropy extraction in power constrained applications.

Method and apparatus for a wafer level system

Abstract: An improved wafer scale integrated circuit is described which includes non-contact power and data transmission coupling. Wireless power and data coupling reduces the mechanical stresses and strains on the wafer, and makes better use of the wafer area. An additional benefit comes from allowing better heat transfer management. In one embodiment, power is provided by inductive coupling. Data flow into and out of the wafer is accomplished optically, using optical detectors to receive and light emitting diodes to transmit. Multiple devices are integrated onto the semiconductor wafer. Systems may be incorporated using the traditional die sites. Connections between systems are made in the space between die sites.