Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Process compensated delay line

Abstract: An integrated circuit that equalizes delay across process corners. A delay equalizer circuit is used to adjust and maintain a relatively constant delay across different process corners. The delay equalizer circuit includes a process monitor and a delay compensator circuit coupled to the process monitor. The process monitor may output a compensating bias voltage for a pMOS transistor and a compensating bias voltage for an nMOS transistor. The compensating bias voltages may be used to regulate and maintain a relatively constant delay through the delay compensator circuit across varying process corners.

A Temperature and Process Corner Insensitive Design Method for Digital Circuits in 40nm CMOS

Abstract: This paper proposes a digital design method enabling a constant path delay across temperature and process corners in 40nm CMOS. Thus, timing analysis and logic synthesis is simplified significantly. The temperature dependency is eliminated by operating at the zero temperature coefficient supply voltage. Additionally, process corner adaptive body biasing compensates process corner dependent path delays. Extensive transistor level simulations for various standard cells show constant path delays across temperature and 6σ process corners. All applied body bias voltages lie within the transistor reliability. This method enables rapid digital synthesis without time consuming process and temperature analyses and optimization.

A Robust Low Power Carbon Nanotube Sensor Interface Circuit in 180 nm CMOS Technology

Abstract: The design and performance of a low-cost, energy-efficient carbon nanotube sensor interface circuit (SIC) is presented that is aimed at deployable/expendable applications with the sensor operating at ambient temperatures. The submicrometer SIC is designed and fabricated in CMOS 180-nm technology and consumes a maximum of 122 μW, including a decoder and voltage follower. The SIC achieves a measurement accuracy of 1.4% over a 2.5 kΩ to 25 MΩ dynamic range of sensor resistance. A critical issue associated with a submicrometer integrated circuit implementation is satisfactory performance of the SIC for fabrication process variations that range from the slow, to typical, to fast process corners and simultaneously meeting the requirement for the very large dynamic range for sensor resistances. A robust design considering the full range of potential process variations becomes more critical as feature size is reduced. The SIC design includes an added degree for freedom for counteracting process variations during post fabrication calibration. In addition, a new design procedure is outlined and implemented to permit an accurate and efficient first order design to ensure satisfactory performance for typical, fast, and slow model parameters. The first order design is verified by complete model simulation performance, and finally selected measured results are included for a fabricated circuit.

Electrical characterization of USB2 multiplexers/BC1.2 power switches/charging modules for accurate channel simulation

Abstract: This paper presents a new methodology of modeling multiplexers (MUXs), power switches and charging modules used in the USB2 interfaces. The proposed method yields a quick and accurate representation in both the time and frequency domains which closely matches the results obtained in both simulation and post-silicon measurement. This will be proven in 2 characterization methods; a time-domain channel response and a frequency domain s-parameter response. The proposed method also produces accurate correlation results across varying topologies, process corners and voltage levels. Subsequently, the method seeks to allow the flexibility of modeling these discrete devices to be used in a Design-of-Experiment (DOE) environment. Ultimately, this translates into a time saving benefit as shorter design cycle times are enabled due to the increased correlation and confidence between pre-silicon simulation and post-silicon validation data.

A 2.4-GHz frequency synthesizer based on process and temperature compensated ring ILFD

Abstract: In this paper, a 2.4-GHz frequency synthesizer incorporating a ring-oscillator based process and temperature compensated injection-locked frequency divider (ILFD) is proposed. The synthesizer is implemented in a 0.18-μm standard complementary metal-oxide semiconductor process with a chip area of 3 mm × 3 mm plus the off-chip capacitors for loop filter. With an LC oscillator, the output frequency can be tuned from 2.057 to 2.652 GHz, while the settling time is around 36 μs with a loop bandwidth of 60 kHz. Measurements are performed across six different chips to study the circuit performance due to process variation. The worst-case total power consumption is measured to be 2.2 mW with a power supply of 1.8 V. The ILFD block is also tested separately and the test results show a wide locking range of 1.4 GHz over all the process corners and a temperature range from 0 to 80 °C.