Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Temperature detecting circuit applied to radio frequency receiver

Abstract: The invention belongs to the technical field of integrated circuit temperature and particularly relates to a temperature detecting circuit applied to a radio frequency receiver The temperature detecting circuit comprises two operational amplifiers and five resistors One operational amplifier and two resistors form a standard voltage generating circuit One operational amplifier and three resistors form a temperature detecting core circuit The standard voltage generating circuit and the temperature detecting core circuit achieve a function of outputting voltage in direct proportion with absolute temperature The temperature detecting circuit adopts a simple structure to achieve a temperature detecting function of a system on a chip and is not sensitive to process corners

A process variation tolerant DLL-based UWB frequency synthesizer

Abstract: A calibration technique for compensation of the generated phase error at the band hopping instant is proposed for a fast-hopping DLL-based injection-locked frequency synthesizer for WiMedia UWB band group #1. This technique makes the accuracy of the phase error compensation immune to process variations and so the VCDL nonlinearity. Simulated in 65-nm CMOS technology, the average synthesizer hopping time is 4 ns for all process corners. The phase noise performance at 1 MHz offset from 4488 MHz carrier is −121 dBc/Hz and the adjacent spur level from the Monte Carlo simulation is −37 dBc. Excluding the CML divider, the synthesizer consumes 7.7 mW from a 1.2 V supply.

A dynamic power-aware process variation calibration scheme

Abstract: In this paper, a power-aware process variation calibration scheme is proposed The proposed calibration system provides the ability to detect and control the n- and p-type variations independently through the use of all-n and all-p ring oscillators Calibration is then carried out through the use of the supply voltage and body bias to alter the device parameters to match those of a certain process corner that is determined by the system designer This scheme is characterized by its ability to dynamically change the desired mapping target according to the computational load The calibration system has been implemented and simulated in TSMC 90-nm technology Simulation results show that the maximum variation in the operating frequency was reduced from 443% to 31% and worst-case leakage current reduced by 21% The results also show the system's ability to compensate for dynamic load variations

Accurate gate delay extraction for timing analysis of body-biased circuits

Abstract: Static body biasing is a circuit technique in which bias voltage is selected from more than one available voltage after manufacturing. It allows circuits to be designed at more favorable process corners; but effective application requires gate delays to be available for the new process corners, without the expense of re-characterizing individual gates. We show that the new delay of a gate (when body bias is applied) can be extrapolated from its old delay without body bias together with old and new delays of a few reference gates. Output transition time, which is another component of gate timing model, is extrapolated in a similar manner. Experiments with an industrial 32-nm gate library show that the average error in the new gate delays is less than 4.3%.

Pulse Broadening in Combinational Circuits with Standard Logic Cell Synthesis

Abstract: Technology scaling improves the power, area, and speed of an electronic design, but the reliability of newer technologies is impacted by the presence of radiation-induced transients; these transients are more pronounced in newer technologies. In the presence of variations due to process corners (P), operating voltage (V), and temperature (T), a transient pulse with no serious threat, which would be masked electrically, traverses more gates towards a storage element due to pulse broadening. In this paper, the transient pulses that initially pose no significant threat are simulated with PVT variations in arithmetic circuits from the EPFL benchmark suite to investigate the effect of variations on vulnerable gates. The results show that the variation enhances the transient pulses with no serious threat and causes pulse broadening from the locations of vulnerable gates. A mitigation approach is applied on the vulnerable gates of the sine circuit, and the masking capability during worst-case analysis improves on average by 76.5% for process corner variation, 85.5% for operating voltage variation, and 84.4% for temperature variation.