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Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.


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Book ChapterDOI
01 Jan 2019
TL;DR: A new high-speed dynamic latched type comparator with reliable resolution that can detect the very low voltage differences such as ±200 µV at the output nodes, reliably is presented in this paper.
Abstract: A new high-speed dynamic latched type comparator with reliable resolution is presented in this paper. The proposed paper presents a 1 GS/s sampling rate in presence of 8 mV input offset, and it can detect the very low voltage differences such as ±200 µV at the output nodes, reliably. The power consumption and delay time of the proposed circuit are 750 µw and 257 ps with the power supply of 1.8 V, respectively. Furthermore, the proposed structure is the suitable candidate for high-speed SAR ADC, as well. Simulation results of the suggested circuit are performed using the BSIM3 model of a 0.18 µm CMOS process with the power supply of 1.8 V at all process corners along with the different temperatures in the region −50 to +50 °C, reliably.

2 citations

Proceedings ArticleDOI
01 Dec 2015
TL;DR: Significant findings were concluded that by changing the options in HSPICE, the accuracy can still be maintained even if the simulation time was reduced.
Abstract: This study aims to create a performance analysis on HSPICE with respect to accuracy and simulation time through the use of HSPICE options Specifically, the suitability of the use of HSPICE as a single simulation platform for both functional and performance simulation coverage have been evaluated Three test circuits have been categorically selected, namely combinational logic, sequential logic and analog for the performance of this tool Accordingly, HSPICE options were pre-determined by using HSPICE User Guide: Simulation and Analysis and tested with respect to the first three process corners (TT, SS and FF) Significant findings were concluded that by changing the options in HSPICE, the accuracy can still be maintained even if the simulation time was reduced

2 citations

Proceedings ArticleDOI
01 Jan 2020
TL;DR: The usage of an auxiliary MOSFET mechanism and storage capacitors to eliminate threshold voltage effect in MOS transistor is recommended, which drastically increases the DC extraction capability of charge pump.
Abstract: In this paper, a cross coupled rectifier is proposed and studied for Radio Frequency (RF) energy harvesting with wide frequency range. Threshold voltage of the MOS transistor is one of the major barriers of RF to DC converter. In this work the usage of an auxiliary MOSFET mechanism and storage capacitors to eliminate threshold voltage effect in MOS transistor is recommended, which drastically increases the DC extraction capability of charge pump. The proposed rectifier is designed and simulated in 90 nm CMOS process and simulation results exhibit a high power conversion efficiency (PCE) of 78.5% for $10 k \Omega$ load. The proposed circuit also gives a same output voltage from 915 MHz to 2.45 GHz. The results also show that the rectifier is insensitive to temperature and process corners. The rectifier can be used in numerous RF energy harvesting system, including RFID applications and other wireless applications.

2 citations

Proceedings ArticleDOI
09 Aug 2021
TL;DR: In this article, a linearization technique for differential transconductors in fully depleted silicon-on-insulator (FD-SOI) CMOS technology is presented, which yields excellent linearity beyond 85 dBc under a considerable input voltage 1 Vppd and is highly applicable in high-bandwidth and wide-swing GmC based Sigma-Delta converters.
Abstract: This paper presents a linearization technique for differential transconductors in fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Dynamic self-biasing is employed at the back-gate node thereby compensating the non-linearity of the main differential input pair. The method yields excellent linearity beyond 85 dBc under a considerable input voltage 1 Vppd and is highly applicable in high-bandwidth and wide-swing GmC based Sigma-Delta converters. The basic principle of the linearization is introduced and proven in a complex ADC architecture. Transistor level simulations show a linearity improvement of 25 dB while only increasing the loop filters power dissipation by 10 %. Process corner, temperature as well as mismatch dependency is evaluated proving the concepts robustness and efficiency.

2 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202311
202226
202138
202047
201943
201864