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Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.


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Proceedings ArticleDOI
Mei Yee Ng1, Yuzman Yusoff1
16 Aug 2010
TL;DR: In this paper, a variable gain potetiostat designed for the electrochemical control of DO sensors is presented, which is targeted for implementation using MIMOS 0.35um CMOS process technology at 3.3V.
Abstract: This paper presents a variable gain potetiostat designed for the electrochemical control of Dissolved Oxygen (DO) sensors. The design is targeted for implementation using MIMOS 0.35um CMOS process technology at 3.3V. The potentiostat amplifier for dissolved oxygen utilizes three electrodes (working, reference and counter) which work together to form the electrochemical reaction. There are several types of DO sensor available including membrane-based, also known as Clark electrode, and microelectrode-based. This results in different sensitivity and output current when different types of sensor are used on the same test solution. The variable gain feature is added in the design to cater to different DO sensors that are available in the market. This design implements four different gain values to accommodate four different current ranges. The resistor values chosen largely depend on the type of DO sensor used and the range of output current it produces. The transimpedance amplifier used has also been simulated in the post-extracted view across process corners to ensure its compatibility with the different feedback resistor values. The complete integrated design is then simulated to be working within a power supply of 2.2V to 3.6V, temperature of 0 to 90°C and has an operating range of 0 to 100uA sensor current. The final chip has an area of 1.7mm × 1.7mm and has been simulated to be in working order.

2 citations

Proceedings ArticleDOI
28 Oct 2002
TL;DR: A 10-bit pipeline ADC is presented using double sampling technique to achieve a conversion rate of 40 MS/s at 2.5-V supply and has differential nonlinearity (DNL) of less than 0.4LSB and achieves 59.1 dB SNDR for 19.9 MHz sinusoidal inputs.
Abstract: This paper presents a 10-bit pipeline ADC using double sampling technique to achieve a conversion rate of 40 MS/s at 2.5-V supply. The opamps are two-stage with folded-cascode as the first stage and feature techniques such as common-mode stabilized active load, cross-coupled cascode connection, and close-loop poles placement. MOS switches are driven by bootstrapping circuits that do not subject the devices to large, terminal voltages. The circuit layout is being completed and the chip will be fabricated in a 0.5-/spl mu/m CMOS technology. Simulation results have been checked for all process corners and including the effect of 3/spl sigma/ capacitor mismatch, comparator offset, 10% variation in poly-poly capacitor size and temperature varying from 0/spl deg/C to 70/spl deg/C. The results show that the converter has differential nonlinearity (DNL) of less than 0.4LSB and achieves 59.1 dB SNDR for 19.9 MHz sinusoidal inputs. Power consumption is estimated at 30.5 mW.

2 citations

Journal ArticleDOI
TL;DR: The effect of temperature and supply voltage (Vdd) on the stability parameters of SRAM which is Static Noise Margin, Write Margin (WM) and Read Current is analyzed.
Abstract: Due to the continuous rising demand of handheld devices like iPods, mobile, tablets; specific applications like biomedical applications like pacemakers, hearing aid machines and space applications which require stable digital systems with low power consumptions are required. As a main part in digital system the SRAM (Static Random Access Memory) should have low power consumption and stability. As we are continuously moving towards scaling for the last two decades the effect of this is process variations which have severe effect on stability, performance. Reducing the supply voltage to sub-threshold region, which helps in reducing the power consumption to an extent but side by side it raises the issue of the stability of the memory. Static Noise Margin of SRAM cell enforces great challenges to the sub threshold SRAM design. In this paper we have analyzed the cell stability of 9T SRAM Cell at various processes. The cell stability is checked at deep submicron (DSM) technology. In this paper we have analyzed the effect of temperature and supply voltage (Vdd) on the stability parameters of SRAM which is Static Noise Margin (SNM), Write Margin (WM) and Read Current. The effect has been observed at various process corners at 45 nm technology. The temperature has a significant effect on stability along with the Vdd. The Cell has been working efficiently at all process corners and has 50% more SNM from conventional 6T SRAM and 30% more WM from conventional 6T SRAM cell.

2 citations

Patent
28 Jan 2015
TL;DR: In this article, the authors proposed a circuit and a method for keeping constant threshold voltage of an MOS (Metal Oxide Semiconductor) transistor, where the voltage feedback circuit is used for adjusting gate end voltage according to substrate voltage Vbulk generated by the charge pump circuit, and the power consumption and the performance of the circuit can be kept in a relative stable state during temperature change and process corner deviation.
Abstract: The invention relates to a circuit and a method for keeping constant threshold voltage of an MOS (Metal Oxide Semiconductor) transistor. The circuit comprises a reference voltage generation circuit, a first comparator, a second comparator, a logic control circuit, a charge pump circuit, a voltage feedback circuit and a clock generation circuit, wherein the voltage feedback circuit is used for adjusting gate end voltage Vg according to substrate voltage Vbulk generated by the charge pump circuit. According to the circuit and the method, the technical problem that the threshold voltage of the existing MOS transistor changes along with a process corner and temperature is solved, and the power consumption and the performance of the circuit can be kept in a relative stable state during temperature change and process corner deviation.

2 citations

Proceedings ArticleDOI
10 Dec 2002
TL;DR: A 10-bit, current-steering, high-speed CMOS D/A converter is presented using a delay technique to increase the speed of the converter and simulation results show that the spurious-free-dynamic-range (SFDR) is better than 62 dB for sampling frequency up to 400 MSample/s and signals from DC to Nyquist.
Abstract: A 10-bit, current-steering, high-speed CMOS D/A converter is presented using a delay technique to increase the speed of the converter Simulation results show that the spurious-free-dynamic-range (SFDR) is better than 62 dB for sampling frequency up to 400 MSample/s and signals from DC to Nyquist Monte-Carlo simulations show that differential non-linearity (DNL) and integral non-linearity (INL) are better than 003 least significant bit (LSB) and 024 LSB, respectively The estimated INL-yield is 997% and the design is based on it The converter dissipates less than 250 mW from a 3 V power supply when operating at 400 MHz The circuit has been designed in a standard 06 /spl mu/m-CMOS process The results have been checked with all process corners from -40/spl deg/C to 85/spl deg/C and power supply from 27 V to 33 V

2 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202311
202226
202138
202047
201943
201864