Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

High-precision correcting circuit for band-gap reference voltage source

Abstract: The invention discloses a high-precision correcting circuit for a band-gap reference voltage source. The circuit includes an operational amplifier, a capacitor, a PMOS tube and a trimming circuit. The opposite phase end of the operational amplifier is connected with reference voltage VBG generated by the band-gap reference voltage source, the in-phase end of the operational amplifier is connected with a first terminal Vf of the trimming circuit, and the output end of the operational amplifier is connected with a first terminal of the capacitor and a grid electrode of the PMOS tube; a source electrode of the PMOS tube is connected with an electric source VDD, a drain electrode of the PMOS tube is connected with a second terminal of the capacitor and a second terminal Vtop of the trimming circuit, a third terminal V1.2 of the trimming circuit is output voltage after correcting, and a fourth terminal Vbottom of the trimming circuit is connected with the ground. According to the high-precision correcting circuit for the band-gap reference voltage source, a snubber circuit in the band-gap reference voltage source is integrated with the correcting circuit, errors caused by influences of process corners, imbalance, temperature and other factors in the reference voltage can be corrected, the influences caused by fine adjustment on the temperature features of the reference voltage can be eliminated and the load carrying capacity of the output voltage is improved. By adopting a digital trimming mode, the high-precision correcting circuit has the advantages of being flexible in correcting, high in precision, low in power consumption and small in area.

Analysis and design of a DC to 18 GHz 6-bit attenuator with simultaneous phase and gain error correction

Abstract: In this paper the design of a digital step attenuator with simultaneous low phase and gain error characteristics is investigated. First, the loading effect of the consecutive blocks of an N-bit attenuator on the precision of the attenuation levels is analyzed. Then a modified structure to decrease the loading effect as well as the phase error of the attenuator blocks is presented. A comprehensive analysis of the circuit is performed and some design guidelines have described. Finally, a 6-bit attenuator with attenuation range of 0.5–31.5 dB and resolution of 0.5 dB is implemented in 0.18 µm complementary metal–oxide-semiconductor (CMOS) technology. The root mean square (RMS) gain error and RMS phase error of the designed circuit for different process corners and DC to 18 GHz are below 0.59 dB and 4.2°, respectively.

Design and implementation of an improved constant-Gm bias circuit

Abstract: Automatic frequency tuning circuit of on-chip Gm-C filter has so many problems such as complex structure, high power consumption and low precision. In order to solve these problems, an improved constant-Gm bias circuit was designed in this paper. The circuit has been analyzed theoretically in detail. Simulation results show that the circuit simplified the structure of frequency tuning circuit, circuit area and power dissipation are reduced, and the deviation is less than 6.5% under different process corners and large temperature variation range. The circuit was applied to the 7th order low pass filter for wireless sensor chips.

High Precision Voltage Monitoring Technology for Multi-cell Battery Management System

Abstract: In order to effectively monitor the battery usage status of electric vehicle, this paper designs a high-precision voltage monitoring circuit applied to multi-series battery packs, which based on the 0.18μm, 40V high voltage BCD process. According to the characteristics of the voltage superposition and battery distinction in the series battery pack, this circuit uses the voltage conversion circuit with the matched negative feedback technology to achieve effective “scaling” of the battery's absolute high voltage to ground-based analog signals. Under the typical/slow/fast process corners, -40°C~85°C and1.5V~31.5V, the simulation results show that the monitoring error of single cell voltage is 1.92mV, and the relative error rate is less than 0.043%, showing out of the strong robustness.

DSDPC: Delay signatures at different process corners based hardware trojan detection technique for FPGAs

Abstract: In applications such as nuclear power plant, space and military, safety critical systems play an important role, where security is one of the crucial design parameters. Similar to software Trojans (virus), Hardware Trojans (HT) are raising security concerns in recent years. HTs are malicious additions or modifications to existing circuit elements which are implemented either as always on or triggered only under certain conditions, to disable functionality, reduce reliability and leak valuable information from the integrated chip. In this paper, we consider the scenario of HTs inserted in field programmable gate array (FPGA) devices during field operating conditions and propose a delay signature based HT detection technique. Static timing analysis is performed to measure the delay signatures of original netlist with that of netlist extracted from field configuration bit file. Since the results of electronic design automation tools are repetitive, we compare both the delay signatures and any deviation will indicate that configuration bit file/ netlist file of the original design is altered. To increase the detection efficiency, we perform static timing analysis at various process corners such as slow, typical and fast corners (at different voltage and temperature combinations) which allows us to measure the best and worst circuit delay values. Using this property, we performed simulations with Xilinx ISE tool by targeting standard benchmark circuits on Xilinx device. Experimental results reflected the difference in delay signatures if configuration bit file is tampered with in the field. The delay difference between with and without HT circuit is enhanced from slow to fast process corner, which in turn increased the HT detection efficiency.